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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-21 11:35:29 +0800 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-21 11:35:29 +0800 |
| commit | ada98844b93e29fcbcfada02f89b2882d73182f1 (patch) | |
| tree | 771a9ef656dacf531074bc3610d78a40b12b0714 /techlibs/greenpak4 | |
| parent | 6b526e93823a72e1b3b2c20a084073477aba399f (diff) | |
| download | yosys-ada98844b93e29fcbcfada02f89b2882d73182f1.tar.gz yosys-ada98844b93e29fcbcfada02f89b2882d73182f1.tar.bz2 yosys-ada98844b93e29fcbcfada02f89b2882d73182f1.zip | |
greenpak4: Added INT pin to GP_SPI
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index a75ea3fe6..dd21bdd50 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -596,10 +596,12 @@ module GP_SPI( input[7:0] TXD_HIGH, input[7:0] TXD_LOW, output reg[7:0] RXD_HIGH, - output reg[7:0] RXD_LOW); + output reg[7:0] RXD_LOW, + output reg INT); initial DOUT_HIGH = 0; initial DOUT_LOW = 0; + initial INT = 0; parameter DATA_WIDTH = 8; //byte or word width parameter SPI_CPHA = 0; //SPI clock phase |