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authorLarry Doolittle <ldoolitt@recycle.lbl.gov>2019-02-24 22:09:54 -0800
committerClifford Wolf <clifford@clifford.at>2019-02-26 09:40:46 -0800
commit7a40294e93490fa462343244b1e2881c3c249c3f (patch)
treedfe0e978253f79363cad090544c3a92c51d65e7a /techlibs/greenpak4
parent61fc411c5d7237e420ee6eb9f6eb093e70d1007d (diff)
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techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module
Diffstat (limited to 'techlibs/greenpak4')
-rw-r--r--techlibs/greenpak4/cells_map.v44
1 files changed, 22 insertions, 22 deletions
diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v
index b971a51fa..51c85183d 100644
--- a/techlibs/greenpak4/cells_map.v
+++ b/techlibs/greenpak4/cells_map.v
@@ -112,14 +112,14 @@ module GP_OBUFT(input IN, input OE, output OUT);
endmodule
module \$lut (A, Y);
- parameter WIDTH = 0;
- parameter LUT = 0;
+ parameter WIDTH = 0;
+ parameter LUT = 0;
- input [WIDTH-1:0] A;
- output Y;
+ input [WIDTH-1:0] A;
+ output Y;
- generate
- if (WIDTH == 1) begin
+ generate
+ if (WIDTH == 1) begin
if(LUT == 2'b01) begin
GP_INV _TECHMAP_REPLACE_ (.OUT(Y), .IN(A[0]) );
end
@@ -127,22 +127,22 @@ module \$lut (A, Y);
GP_2LUT #(.INIT({2'b00, LUT})) _TECHMAP_REPLACE_ (.OUT(Y),
.IN0(A[0]), .IN1(1'b0));
end
- end else
- if (WIDTH == 2) begin
- GP_2LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
- .IN0(A[0]), .IN1(A[1]));
- end else
- if (WIDTH == 3) begin
- GP_3LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
- .IN0(A[0]), .IN1(A[1]), .IN2(A[2]));
- end else
- if (WIDTH == 4) begin
- GP_4LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
- .IN0(A[0]), .IN1(A[1]), .IN2(A[2]), .IN3(A[3]));
- end else begin
- wire _TECHMAP_FAIL_ = 1;
- end
- endgenerate
+ end else
+ if (WIDTH == 2) begin
+ GP_2LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
+ .IN0(A[0]), .IN1(A[1]));
+ end else
+ if (WIDTH == 3) begin
+ GP_3LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
+ .IN0(A[0]), .IN1(A[1]), .IN2(A[2]));
+ end else
+ if (WIDTH == 4) begin
+ GP_4LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
+ .IN0(A[0]), .IN1(A[1]), .IN2(A[2]), .IN3(A[3]));
+ end else begin
+ wire _TECHMAP_FAIL_ = 1;
+ end
+ endgenerate
endmodule
module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);