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author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-09-01 06:41:39 -0700 |
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committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-09-01 06:45:10 -0700 |
commit | 40021d2fd89281277da1dfa31896911cc18748d7 (patch) | |
tree | 00c8d9ec51e325614ab0af92f575ca81d908b75e /techlibs/greenpak4 | |
parent | fc0c7f74dc9133bbf19aa9eafff26738a05135ef (diff) | |
download | yosys-40021d2fd89281277da1dfa31896911cc18748d7.tar.gz yosys-40021d2fd89281277da1dfa31896911cc18748d7.tar.bz2 yosys-40021d2fd89281277da1dfa31896911cc18748d7.zip |
Fixed typo in error message
Diffstat (limited to 'techlibs/greenpak4')
-rw-r--r-- | techlibs/greenpak4/cells_sim_digital.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index b87795ceb..43d35d08f 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -102,7 +102,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT); default: begin initial begin - $display("Invalid RESET_MODE on GP_COUNT8"); + $display("Invalid RESET_MODE on GP_COUNT14"); $finish; end end |