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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 17:15:56 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-15 09:18:27 -0700 |
| commit | 3a404be62a7b7fcc435857e20aa6c528f373b81c (patch) | |
| tree | 34157f9c4aea862a823e86a334784b465c7128ff /techlibs/greenpak4 | |
| parent | e5109847c9a6c4b34a2d78442758773adfea2f4f (diff) | |
| download | yosys-3a404be62a7b7fcc435857e20aa6c528f373b81c.tar.gz yosys-3a404be62a7b7fcc435857e20aa6c528f373b81c.tar.bz2 yosys-3a404be62a7b7fcc435857e20aa6c528f373b81c.zip | |
Updated PGEN model to have level triggered reset (matches actual hardware behavior
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim_digital.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index 5d9d67750..6fba941a0 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -741,10 +741,10 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT); localparam COUNT_MAX = PATTERN_LEN - 1'h1; reg[3:0] count = 0; - always @(posedge CLK) begin - if(!nRST) begin - count <= COUNT_MAX; - end + always @(posedge CLK, negedge nRST) begin + + if(!nRST) + count <= 0; else begin count <= count - 1'h1; |