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author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 16:28:59 -0700 |
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committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-15 09:18:17 -0700 |
commit | e5109847c9a6c4b34a2d78442758773adfea2f4f (patch) | |
tree | 6438a5eafbc1d4df6d3533bc0d635110063b2624 /techlibs/greenpak4/cells_sim_digital.v | |
parent | 66b256d40e8762abd1c43e1c5d37d93fb57fc84e (diff) | |
download | yosys-e5109847c9a6c4b34a2d78442758773adfea2f4f.tar.gz yosys-e5109847c9a6c4b34a2d78442758773adfea2f4f.tar.bz2 yosys-e5109847c9a6c4b34a2d78442758773adfea2f4f.zip |
Fixed bug in GP_COUNTx model
Diffstat (limited to 'techlibs/greenpak4/cells_sim_digital.v')
-rw-r--r-- | techlibs/greenpak4/cells_sim_digital.v | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index 84a5dd049..5d9d67750 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -147,10 +147,11 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, if(KEEP) begin end - else if(UP) + else if(UP) begin count <= count + 1'd1; if(count == 14'h3fff) count <= COUNT_TO; + end else begin count <= count - 1'd1; @@ -174,10 +175,11 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, if(KEEP) begin end - else if(UP) + else if(UP) begin count <= count + 1'd1; if(count == 14'h3fff) count <= COUNT_TO; + end else begin count <= count - 1'd1; @@ -218,10 +220,11 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, if(KEEP) begin end - else if(UP) + else if(UP) begin count <= count + 1'd1; if(count == 14'h3fff) count <= COUNT_TO; + end else begin count <= count - 1'd1; @@ -284,10 +287,11 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, //Main counter if(KEEP) begin end - else if(UP) + else if(UP) begin count <= count + 1'd1; if(count == 8'hff) count <= COUNT_TO; + end else begin count <= count - 1'd1; @@ -312,10 +316,11 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, //Main counter if(KEEP) begin end - else if(UP) + else if(UP) begin count <= count + 1'd1; if(count == 8'hff) count <= COUNT_TO; + end else begin count <= count - 1'd1; @@ -356,17 +361,17 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, if(KEEP) begin end - else if(UP) + else if(UP) begin count <= count + 1'd1; if(count == 8'hff) count <= COUNT_TO; + end else begin count <= count - 1'd1; if(count == 0) count <= COUNT_TO; end - end end |