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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-05-04 17:03:45 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-05-04 17:03:45 -0700 |
| commit | dee1c27a19f91fb44df67b2ab9834ee8140772c4 (patch) | |
| tree | 22f3b9613f0673adf2c9358865fd82db44462b84 /techlibs/greenpak4/cells_sim.v | |
| parent | a613f171aeb8703b6849a87b73899389fb9912d8 (diff) | |
| download | yosys-dee1c27a19f91fb44df67b2ab9834ee8140772c4.tar.gz yosys-dee1c27a19f91fb44df67b2ab9834ee8140772c4.tar.bz2 yosys-dee1c27a19f91fb44df67b2ab9834ee8140772c4.zip | |
Renamed module parameter
Diffstat (limited to 'techlibs/greenpak4/cells_sim.v')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 6c3ffcaa0..6cf29fe6e 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -278,9 +278,9 @@ endmodule module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB); - parameter OUTA_DELAY = 1; + parameter OUTA_TAP = 1; parameter OUTA_INVERT = 0; - parameter OUTB_DELAY = 1; + parameter OUTB_TAP = 1; reg[15:0] shreg = 0; @@ -294,8 +294,8 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB); end - assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_DELAY - 1] : shreg[OUTA_DELAY - 1]; - assign OUTB = shreg[OUTB_DELAY - 1]; + assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1]; + assign OUTB = shreg[OUTB_TAP - 1]; endmodule |