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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-01 21:18:29 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-01 21:18:29 -0700 |
| commit | 2386885f228ebecccf4987ac81bde11df56dae38 (patch) | |
| tree | 3cb1f031f18eba3f09fa7fd2087a58f6ddfb3220 /techlibs/greenpak4/cells_sim.v | |
| parent | b0a28c793cebcd1a7317b63b215151ce9ace3a42 (diff) | |
| download | yosys-2386885f228ebecccf4987ac81bde11df56dae38.tar.gz yosys-2386885f228ebecccf4987ac81bde11df56dae38.tar.bz2 yosys-2386885f228ebecccf4987ac81bde11df56dae38.zip | |
Added GreenPak inverter support
Diffstat (limited to 'techlibs/greenpak4/cells_sim.v')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 2727d9246..4ea576960 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -40,6 +40,10 @@ module GP_DFFSR(input D, CLK, nSR, output reg Q); end endmodule +module GP_INV(input IN, output OUT); + assign OUT = ~IN; +endmodule + module GP_2LUT(input IN0, IN1, output OUT); parameter [3:0] INIT = 0; assign OUT = INIT[{IN1, IN0}]; |