aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/gowin/lutrams.txt
diff options
context:
space:
mode:
authorwhitequark <whitequark@whitequark.org>2020-01-01 12:30:00 +0000
committerwhitequark <whitequark@whitequark.org>2020-01-01 12:30:00 +0000
commit550310e2647c7aac1e49b79d9ff912436103062f (patch)
tree7627eab28fcd68104522d1623108ebb478c9aa84 /techlibs/gowin/lutrams.txt
parent22fe931c861aa3f557327baf9d12ec57006308d9 (diff)
downloadyosys-550310e2647c7aac1e49b79d9ff912436103062f.tar.gz
yosys-550310e2647c7aac1e49b79d9ff912436103062f.tar.bz2
yosys-550310e2647c7aac1e49b79d9ff912436103062f.zip
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
Diffstat (limited to 'techlibs/gowin/lutrams.txt')
-rw-r--r--techlibs/gowin/lutrams.txt17
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/gowin/lutrams.txt b/techlibs/gowin/lutrams.txt
new file mode 100644
index 000000000..9db530251
--- /dev/null
+++ b/techlibs/gowin/lutrams.txt
@@ -0,0 +1,17 @@
+bram $__GW1NR_RAM16S4
+ init 1
+ abits 4
+ dbits 4
+ groups 2
+ ports 1 1
+ wrmode 0 1
+ enable 0 1
+ transp 0 1
+ clocks 0 1
+ clkpol 0 1
+endbram
+
+match $__GW1NR_RAM16S4
+ make_outreg
+ min wports 1
+endmatch