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author | Eddie Hung <eddie@fpgeh.com> | 2019-12-27 12:15:33 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 14:36:07 -0800 |
commit | 543bd2de6c00f98577263439ebdada7bcda249ab (patch) | |
tree | 882288201f133f89021d9b4a6f2339056509e57b /techlibs/gowin/determine_init.cc | |
parent | c0a17c2457532726b05586d3b7a030bd9f372dea (diff) | |
download | yosys-543bd2de6c00f98577263439ebdada7bcda249ab.tar.gz yosys-543bd2de6c00f98577263439ebdada7bcda249ab.tar.bz2 yosys-543bd2de6c00f98577263439ebdada7bcda249ab.zip |
Update timings for Xilinx S7 cells
Diffstat (limited to 'techlibs/gowin/determine_init.cc')
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