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author | Patrick Urban <patrick.urban@web.de> | 2021-09-24 16:00:59 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-11-13 21:53:25 +0100 |
commit | 0a72952d5f259a23f9d1122d936d3d4d60ce224d (patch) | |
tree | 45c12931e95aade5618088a70d2f0187bd1fdeb2 /techlibs/gatemate/reg_map.v | |
parent | cfcc38582a4464b0a0551b842ea7a22c6f9a559d (diff) | |
download | yosys-0a72952d5f259a23f9d1122d936d3d4d60ce224d.tar.gz yosys-0a72952d5f259a23f9d1122d936d3d4d60ce224d.tar.bz2 yosys-0a72952d5f259a23f9d1122d936d3d4d60ce224d.zip |
synth_gatemate: Apply review remarks
* remove unused techmap models in `map_regs.v`
* replace RAM initilization loops with 320-bit-writes
* add script to test targets in top-level Makefile
* remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v`
* iterate over all modules in `gatemate_bramopt` pass
Diffstat (limited to 'techlibs/gatemate/reg_map.v')
-rw-r--r-- | techlibs/gatemate/reg_map.v | 61 |
1 files changed, 0 insertions, 61 deletions
diff --git a/techlibs/gatemate/reg_map.v b/techlibs/gatemate/reg_map.v index 5075adf03..8dc4f672f 100644 --- a/techlibs/gatemate/reg_map.v +++ b/techlibs/gatemate/reg_map.v @@ -17,54 +17,6 @@ *
*/
-(* techmap_celltype = "$_DFF_[NP]_" *)
-module \$_DFF_x_ (input D, C, output Q);
-
- parameter _TECHMAP_CELLTYPE_ = "";
-
- CC_DFF #(
- .CLK_INV((_TECHMAP_CELLTYPE_[15:8] == "N")),
- .EN_INV(1'b0),
- .SR_INV(1'b0),
- .SR_VAL(1'b0)
- ) _TECHMAP_REPLACE_ (.D(D), .EN(1'b1), .CLK(C), .SR(1'b0), .Q(Q));
-
- wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-
-endmodule
-
-(* techmap_celltype = "$_DFF_[NP][NP][01]_" *)
-module \$_DFF_xxx_ (input D, C, R, output Q);
-
- parameter _TECHMAP_CELLTYPE_ = "";
-
- CC_DFF #(
- .CLK_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
- .EN_INV(1'b0),
- .SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
- .SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1")
- ) _TECHMAP_REPLACE_ (.D(D), .EN(1'b1), .CLK(C), .SR(R), .Q(Q));
-
- wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-
-endmodule
-
-(* techmap_celltype = "$_DFFE_[NP][NP]_" *)
-module \$_DFFE_xx_ (input D, C, E, output Q);
-
- parameter _TECHMAP_CELLTYPE_ = "";
-
- CC_DFF #(
- .CLK_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
- .EN_INV(_TECHMAP_CELLTYPE_[15:8] == "N"),
- .SR_INV(1'b0),
- .SR_VAL(1'b0)
- ) _TECHMAP_REPLACE_ (.D(D), .EN(E), .CLK(C), .SR(1'b0), .Q(Q));
-
- wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
-
-endmodule
-
(* techmap_celltype = "$_DFFE_[NP][NP][01][NP]_" *)
module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
@@ -81,19 +33,6 @@ module \$_DFFE_xxxx_ (input D, C, R, E, output Q); endmodule
-(* techmap_celltype = "$_DLATCH_[NP]_" *)
-module \$_DLATCH_x_ (input E, D, output Q);
-
- parameter _TECHMAP_CELLTYPE_ = "";
-
- CC_DLT #(
- .G_INV(_TECHMAP_CELLTYPE_[15:8] == "N"),
- .SR_INV(1'b0),
- .SR_VAL(1'b0)
- ) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(1'b0), .Q(Q));
-
-endmodule
-
(* techmap_celltype = "$_DLATCH_[NP][NP][01]_" *)
module \$_DLATCH_xxx_ (input E, R, D, output Q);
|