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| author | clairexen <claire@symbioticeda.com> | 2020-10-20 17:11:36 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-10-20 17:11:36 +0200 |
| commit | e919d0c1255cda47fa5835ad468266621cab0ecf (patch) | |
| tree | 4df3626e791a0368cd103469941701aaac3ce672 /techlibs/efinix | |
| parent | 099d0c2a8ae3c4ef43703afcabf8ce98be124d95 (diff) | |
| parent | 8be56960a26081ab57542d71fb78be594b9e014f (diff) | |
| download | yosys-e919d0c1255cda47fa5835ad468266621cab0ecf.tar.gz yosys-e919d0c1255cda47fa5835ad468266621cab0ecf.tar.bz2 yosys-e919d0c1255cda47fa5835ad468266621cab0ecf.zip | |
Merge pull request #2405 from byuccl/fix_xilinx_cells
xilinx/cells_sim.v: Move signal declaration to before first use
Diffstat (limited to 'techlibs/efinix')
0 files changed, 0 insertions, 0 deletions