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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-03 12:29:30 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-03 13:10:44 +0200 |
| commit | ab98f604fd1319e0f42b0c5dc8bb6be5d3d2ba38 (patch) | |
| tree | dc3f3dcfea09ddc7e49b025d98f85ff29d02a7c4 /techlibs/efinix/cells_sim.v | |
| parent | 0917a5cf720e76a85cd2fa4d8cd3cf9434bdee8f (diff) | |
| download | yosys-ab98f604fd1319e0f42b0c5dc8bb6be5d3d2ba38.tar.gz yosys-ab98f604fd1319e0f42b0c5dc8bb6be5d3d2ba38.tar.bz2 yosys-ab98f604fd1319e0f42b0c5dc8bb6be5d3d2ba38.zip | |
Initial EFINIX support
Diffstat (limited to 'techlibs/efinix/cells_sim.v')
| -rw-r--r-- | techlibs/efinix/cells_sim.v | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v new file mode 100644 index 000000000..aaff955a2 --- /dev/null +++ b/techlibs/efinix/cells_sim.v @@ -0,0 +1,36 @@ +module EFX_LUT4( + output O, + input I0, + input I1, + input I2, + input I3 +); + parameter LUTMASK = 16'h0000; +endmodule + +module EFX_ADD( + output O, + output CO, + input I0, + input I1, + input CI +); + parameter I0_POLARITY = 1; + parameter I1_POLARITY = 1; +endmodule + +module EFX_FF( + output Q, + input D, + input CE, + input CLK, + input SR +); + parameter CLK_POLARITY = 1; + parameter CE_POLARITY = 1; + parameter SR_POLARITY = 1; + parameter SR_SYNC = 0; + parameter SR_VALUE = 0; + parameter SR_SYNC_PRIORITY = 0; + parameter D_POLARITY = 1; +endmodule
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