diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 11:09:42 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 11:09:42 -0700 |
| commit | 4ef26d4755d355e562a173c86d3eace100a266fe (patch) | |
| tree | 6d331a5b3fa83d9072c25f7825cacb4e3d30cea5 /techlibs/ecp5 | |
| parent | 1c79a32276ef4ae3601cb75e0ab05ba1afe4d385 (diff) | |
| parent | da5f83039527bf50af001671744f351988c3261a (diff) | |
| download | yosys-4ef26d4755d355e562a173c86d3eace100a266fe.tar.gz yosys-4ef26d4755d355e562a173c86d3eace100a266fe.tar.bz2 yosys-4ef26d4755d355e562a173c86d3eace100a266fe.zip | |
Merge remote-tracking branch 'origin/master' into xc7mux
Diffstat (limited to 'techlibs/ecp5')
| -rw-r--r-- | techlibs/ecp5/abc_5g.box | 2 | ||||
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 10 |
2 files changed, 5 insertions, 7 deletions
diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box index 5309aca87..c757d137d 100644 --- a/techlibs/ecp5/abc_5g.box +++ b/techlibs/ecp5/abc_5g.box @@ -16,7 +16,7 @@ CCU2C 1 1 9 3 516 516 516 516 412 412 278 278 43 # Box 2 : TRELLIS_DPR16X4 (16x4 dist ram) -# Outputs: DO0, DO1, DO2, DO3, DO4 +# Outputs: DO0, DO1, DO2, DO3 # name ID w/b ins outs TRELLIS_DPR16X4 2 0 14 4 diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 08ae0a112..ca88d0a5b 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -15,11 +15,9 @@ module L6MUX21 (input D0, D1, SD, output Z); endmodule // --------------------------------------- -(* abc_box_id=1, abc_carry, lib_whitebox *) -module CCU2C((* abc_carry_in *) input CIN, - input A0, B0, C0, D0, A1, B1, C1, D1, - output S0, S1, - (* abc_carry_out *) output COUT); +(* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *) +module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1, + output S0, S1, COUT); parameter [15:0] INIT0 = 16'h0000; parameter [15:0] INIT1 = 16'h0000; @@ -106,7 +104,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- -(* abc_box_id=2, abc_scc_break="DI,WRE" *) +//(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *) module TRELLIS_DPR16X4 ( input [3:0] DI, input [3:0] WAD, |