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| author | whitequark <whitequark@whitequark.org> | 2020-01-02 21:06:17 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-02 21:06:17 +0000 |
| commit | f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3 (patch) | |
| tree | e7c5b19ffae2bfc40e682f696d2ae40513717ad7 /techlibs/ecp5/lutrams.txt | |
| parent | ef6548203cca239a98b00ea652a92fe3e20f97d7 (diff) | |
| parent | 550310e2647c7aac1e49b79d9ff912436103062f (diff) | |
| download | yosys-f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3.tar.gz yosys-f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3.tar.bz2 yosys-f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3.zip | |
Merge pull request #1604 from whitequark/unify-ram-naming
Harmonize BRAM/LUTRAM descriptions across all of Yosys
Diffstat (limited to 'techlibs/ecp5/lutrams.txt')
| -rw-r--r-- | techlibs/ecp5/lutrams.txt | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/ecp5/lutrams.txt b/techlibs/ecp5/lutrams.txt new file mode 100644 index 000000000..b94357429 --- /dev/null +++ b/techlibs/ecp5/lutrams.txt @@ -0,0 +1,17 @@ +bram $__TRELLIS_DPR16X4 + init 1 + abits 4 + dbits 4 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +match $__TRELLIS_DPR16X4 + make_outreg + min wports 1 +endmatch |