kernel: big fat patch to use more ID::*, otherwise ID(*)

1 files changed, 22 insertions, 22 deletions

diff --git a/techlibs/ecp5/ecp5_ffinit.cc b/techlibs/ecp5/ecp5_ffinit.cc
index dbd16cac9..e85bee64e 100644
--- a/techlibs/ecp5/ecp5_ffinit.cc
+++ b/techlibs/ecp5/ecp5_ffinit.cc
@@ -63,11 +63,11 @@ struct Ecp5FfinitPass : public Pass {
 
 			for (auto wire : module->selected_wires())
 			{
-				if (wire->attributes.count("\\init") == 0)
+				if (wire->attributes.count(ID::init) == 0)
 					continue;
 
 				SigSpec wirebits = sigmap(wire);
-				Const initval = wire->attributes.at("\\init");
+				Const initval = wire->attributes.at(ID::init);
 				init_wires.insert(wire);
 
 				for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
@@ -94,11 +94,11 @@ struct Ecp5FfinitPass : public Pass {
 			}
 			for (auto cell : module->selected_cells())
 			{
-				if (cell->type != "\\TRELLIS_FF")
+				if (cell->type != ID(TRELLIS_FF))
 					continue;
-				SigSpec sig_d = cell->getPort("\\DI");
-				SigSpec sig_q = cell->getPort("\\Q");
-				SigSpec sig_lsr = cell->getPort("\\LSR");
+				SigSpec sig_d = cell->getPort(ID(DI));
+				SigSpec sig_q = cell->getPort(ID::Q);
+				SigSpec sig_lsr = cell->getPort(ID(LSR));
 
 				if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
 					continue;
@@ -107,8 +107,8 @@ struct Ecp5FfinitPass : public Pass {
 				SigBit bit_q = sigmap(sig_q[0]);
 
 				std::string regset = "RESET";
-				if (cell->hasParam("\\REGSET"))
-					regset = cell->getParam("\\REGSET").decode_string();
+				if (cell->hasParam(ID(REGSET)))
+					regset = cell->getParam(ID(REGSET)).decode_string();
 				State resetState;
 				if (regset == "SET")
 					resetState = State::S1;
@@ -136,8 +136,8 @@ struct Ecp5FfinitPass : public Pass {
 
 				if (GetSize(sig_lsr) >= 1 && sig_lsr[0] != State::S0) {
 					std::string srmode = "LSR_OVER_CE";
-					if (cell->hasParam("\\SRMODE"))
-						srmode = cell->getParam("\\SRMODE").decode_string();
+					if (cell->hasParam(ID(SRMODE)))
+						srmode = cell->getParam(ID(SRMODE)).decode_string();
 					if (srmode == "ASYNC") {
 						log("Async reset value %c for FF cell %s inconsistent with init value %c.\n",
 							resetState != State::S0 ? '1' : '0', log_id(cell), val != State::S0 ? '1' : '0');
@@ -150,14 +150,14 @@ struct Ecp5FfinitPass : public Pass {
 							module->addOrGate(NEW_ID, bit_d, bit_lsr, new_bit_d);
 						}
 
-						cell->setPort("\\DI", new_bit_d);
-						cell->setPort("\\LSR", State::S0);
+						cell->setPort(ID(DI), new_bit_d);
+						cell->setPort(ID(LSR), State::S0);
 
-						if(cell->hasPort("\\CE")) {
+						if(cell->hasPort(ID(CE))) {
 							std::string cemux = "CE";
-							if (cell->hasParam("\\CEMUX"))
-								cemux = cell->getParam("\\CEMUX").decode_string();
-							SigSpec sig_ce = cell->getPort("\\CE");
+							if (cell->hasParam(ID(CEMUX)))
+								cemux = cell->getParam(ID(CEMUX)).decode_string();
+							SigSpec sig_ce = cell->getPort(ID(CE));
 							if (GetSize(sig_ce) >= 1) {
 								SigBit bit_ce = sigmap(sig_ce[0]);
 								Wire *new_bit_ce = module->addWire(NEW_ID);
@@ -165,25 +165,25 @@ struct Ecp5FfinitPass : public Pass {
 									module->addAndnotGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
 								else
 									module->addOrGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
-								cell->setPort("\\CE", new_bit_ce);
+								cell->setPort(ID(CE), new_bit_ce);
 							}
 						}
-						cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
+						cell->setParam(ID(REGSET), val != State::S0 ? Const("SET") : Const("RESET"));
 						handled_initbits.insert(bit_q);
 					}
 				} else {
-					cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
+					cell->setParam(ID(REGSET), val != State::S0 ? Const("SET") : Const("RESET"));
 					handled_initbits.insert(bit_q);
 				}
 			}
 
 			for (auto wire : init_wires)
 			{
-				if (wire->attributes.count("\\init") == 0)
+				if (wire->attributes.count(ID::init) == 0)
 					continue;
 
 				SigSpec wirebits = sigmap(wire);
-				Const &initval = wire->attributes.at("\\init");
+				Const &initval = wire->attributes.at(ID::init);
 				bool remove_attribute = true;
 
 				for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) {
@@ -194,7 +194,7 @@ struct Ecp5FfinitPass : public Pass {
 				}
 
 				if (remove_attribute)
-					wire->attributes.erase("\\init");
+					wire->attributes.erase(ID::init);
 			}
 		}
 	}