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| author | David Shah <davey1576@gmail.com> | 2019-02-19 19:34:37 +0000 |
|---|---|---|
| committer | David Shah <davey1576@gmail.com> | 2019-02-19 19:34:37 +0000 |
| commit | bb56cb738d6586059855cc3deefad12119673157 (patch) | |
| tree | d006d9f383328a8a31991198be6813e88e8e01a4 /techlibs/ecp5/cells_bb.v | |
| parent | c36f15b489c1d47e94901e9286c4f1c2afb815c4 (diff) | |
| download | yosys-bb56cb738d6586059855cc3deefad12119673157.tar.gz yosys-bb56cb738d6586059855cc3deefad12119673157.tar.bz2 yosys-bb56cb738d6586059855cc3deefad12119673157.zip | |
ecp5: Add DDRDLLA
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'techlibs/ecp5/cells_bb.v')
| -rw-r--r-- | techlibs/ecp5/cells_bb.v | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v index bac17260f..223e19b9e 100644 --- a/techlibs/ecp5/cells_bb.v +++ b/techlibs/ecp5/cells_bb.v @@ -309,6 +309,15 @@ module DQSBUFM( endmodule (* blackbox *) +module DDRDLLA( + input CLK, RST, UDDCNTLN, FREEZE, + output LOCK, DDRDEL, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0 +); + parameter FORCE_MAX_DELAY = "NO"; + parameter GSR = "ENABLED"; +endmodule + +(* blackbox *) module CLKDIVF( input CLKI, RST, ALIGNWD, output CDIVX |