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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:54:28 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-18 10:54:28 +0200 |
| commit | b4d765054897f7ee388b54d907fd8ce607db2d58 (patch) | |
| tree | a625838a0efbfb0176a57887c208467a7addd0a6 /techlibs/ecp5/cells_bb.v | |
| parent | b659082e4a72209af62a19668800bb6334a437d7 (diff) | |
| parent | ab4899a2d02b994d79e4aa223eb743793b9a60b3 (diff) | |
| download | yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.tar.gz yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.tar.bz2 yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.zip | |
Merge branch 'master' into mmicko/efinix
Diffstat (limited to 'techlibs/ecp5/cells_bb.v')
| -rw-r--r-- | techlibs/ecp5/cells_bb.v | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v index 0a5046db2..ae124e7a3 100644 --- a/techlibs/ecp5/cells_bb.v +++ b/techlibs/ecp5/cells_bb.v @@ -334,6 +334,13 @@ module ECLKSYNCB( endmodule (* blackbox *) +module ECLKBRIDGECS( + input CLK0, CLK1, SEL, + output ECSOUT +); +endmodule + +(* blackbox *) module DCCA( input CLKI, CE, output CLKO |