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| author | David Shah <dave@ds0.me> | 2018-10-10 17:18:17 +0100 |
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| committer | David Shah <dave@ds0.me> | 2018-10-10 17:18:17 +0100 |
| commit | bdfead8c648db77b9350f941d6578a48bdaa2203 (patch) | |
| tree | df76afe327eb2598ac1c0ea8040128f9f2824fa2 /techlibs/ecp5/brams_map.v | |
| parent | 983fb7ff88ab5f398073e2aa1d5e44eb03d01ee3 (diff) | |
| download | yosys-bdfead8c648db77b9350f941d6578a48bdaa2203.tar.gz yosys-bdfead8c648db77b9350f941d6578a48bdaa2203.tar.bz2 yosys-bdfead8c648db77b9350f941d6578a48bdaa2203.zip | |
ecp5: Adding BRAM maps for all size options
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs/ecp5/brams_map.v')
| -rw-r--r-- | techlibs/ecp5/brams_map.v | 65 |
1 files changed, 64 insertions, 1 deletions
diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v index 894f5c46f..61dee7054 100644 --- a/techlibs/ecp5/brams_map.v +++ b/techlibs/ecp5/brams_map.v @@ -24,7 +24,6 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "NORMAL"; - generate if (CFG_DBITS == 1) begin DP16KD #( `include "bram_init_1_2_4.vh" @@ -41,6 +40,70 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1), .RSTA(1'b0), .RSTB(1'b0) ); + end else if (CFG_DBITS == 2) begin + DP16KD #( + `include "bram_init_1_2_4.vh" + .DATA_WIDTH_A(2), + .DATA_WIDTH_B(2), + .CLKAMUX(CLKAMUX), + .CLKBMUX(CLKBMUX), + .WRITEMODE_A(WRITEMODE_A), + .GSR("DISABLED") + ) _TECHMAP_REPLACE_ ( + `include "bram_conn_2.vh" + .CLKA(CLK2), .CLKB(CLK3), + .WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1), + .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1), + .RSTA(1'b0), .RSTB(1'b0) + ); + end else if (CFG_DBITS <= 4) begin + DP16KD #( + `include "bram_init_1_2_4.vh" + .DATA_WIDTH_A(4), + .DATA_WIDTH_B(4), + .CLKAMUX(CLKAMUX), + .CLKBMUX(CLKBMUX), + .WRITEMODE_A(WRITEMODE_A), + .GSR("DISABLED") + ) _TECHMAP_REPLACE_ ( + `include "bram_conn_4.vh" + .CLKA(CLK2), .CLKB(CLK3), + .WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1), + .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1), + .RSTA(1'b0), .RSTB(1'b0) + ); + end else if (CFG_DBITS <= 9) begin + DP16KD #( + `include "bram_init_9_18_36.vh" + .DATA_WIDTH_A(9), + .DATA_WIDTH_B(9), + .CLKAMUX(CLKAMUX), + .CLKBMUX(CLKBMUX), + .WRITEMODE_A(WRITEMODE_A), + .GSR("DISABLED") + ) _TECHMAP_REPLACE_ ( + `include "bram_conn_9.vh" + .CLKA(CLK2), .CLKB(CLK3), + .WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1), + .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1), + .RSTA(1'b0), .RSTB(1'b0) + ); + end else if (CFG_DBITS <= 18) begin + DP16KD #( + `include "bram_init_9_18_36.vh" + .DATA_WIDTH_A(18), + .DATA_WIDTH_B(18), + .CLKAMUX(CLKAMUX), + .CLKBMUX(CLKBMUX), + .WRITEMODE_A(WRITEMODE_A), + .GSR("DISABLED") + ) _TECHMAP_REPLACE_ ( + `include "bram_conn_18.vh" + .CLKA(CLK2), .CLKB(CLK3), + .WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1), + .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1), + .RSTA(1'b0), .RSTB(1'b0) + ); end else begin wire TECHMAP_FAIL = 1'b1; end endgenerate |