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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 19:18:36 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 19:18:36 -0700 |
commit | d46dc9c5b4362c1e333979cbbac4f3567904fee5 (patch) | |
tree | 1f7b9a765b2def3ca6acf412c1e6282132b582b7 /techlibs/ecp5/abc_map.v | |
parent | 55acf3120fa47bb95be8a6551738f4f9b1c70a21 (diff) | |
download | yosys-d46dc9c5b4362c1e333979cbbac4f3567904fee5.tar.gz yosys-d46dc9c5b4362c1e333979cbbac4f3567904fee5.tar.bz2 yosys-d46dc9c5b4362c1e333979cbbac4f3567904fee5.zip |
ecp5 to use -max_iter 1
Diffstat (limited to 'techlibs/ecp5/abc_map.v')
-rw-r--r-- | techlibs/ecp5/abc_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v index e8187ed18..ffd25f06d 100644 --- a/techlibs/ecp5/abc_map.v +++ b/techlibs/ecp5/abc_map.v @@ -13,7 +13,7 @@ module TRELLIS_DPR16X4 ( parameter [63:0] INITVAL = 64'h0000000000000000; wire [3:0] \$DO ; - \$__ABC_DPR16X4_SEQ #( + TRELLIS_DPR16X4 #( .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL) ) _TECHMAP_REPLACE_ ( .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK), |