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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:54:28 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-18 10:54:28 +0200 |
| commit | b4d765054897f7ee388b54d907fd8ce607db2d58 (patch) | |
| tree | a625838a0efbfb0176a57887c208467a7addd0a6 /techlibs/ecp5/abc9_map.v | |
| parent | b659082e4a72209af62a19668800bb6334a437d7 (diff) | |
| parent | ab4899a2d02b994d79e4aa223eb743793b9a60b3 (diff) | |
| download | yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.tar.gz yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.tar.bz2 yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.zip | |
Merge branch 'master' into mmicko/efinix
Diffstat (limited to 'techlibs/ecp5/abc9_map.v')
| -rw-r--r-- | techlibs/ecp5/abc9_map.v | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/techlibs/ecp5/abc9_map.v b/techlibs/ecp5/abc9_map.v new file mode 100644 index 000000000..d8d70f9f6 --- /dev/null +++ b/techlibs/ecp5/abc9_map.v @@ -0,0 +1,24 @@ +// --------------------------------------- + +module TRELLIS_DPR16X4 ( + input [3:0] DI, + input [3:0] WAD, + input WRE, + input WCK, + input [3:0] RAD, + output [3:0] DO +); + parameter WCKMUX = "WCK"; + parameter WREMUX = "WRE"; + parameter [63:0] INITVAL = 64'h0000000000000000; + wire [3:0] \$DO ; + + TRELLIS_DPR16X4 #( + .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL) + ) _TECHMAP_REPLACE_ ( + .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK), + .RAD(RAD), .DO(\$DO ) + ); + + \$__ABC9_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO)); +endmodule |