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authorMiodrag Milanović <mmicko@gmail.com>2019-10-18 10:51:32 +0200
committerGitHub <noreply@github.com>2019-10-18 10:51:32 +0200
commite0a67fce12647b4db7125d33264847c0a3781105 (patch)
tree38f3dc5651aa6bab8afb3217a90a7c0350ef23ae /techlibs/easic
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parente6ad714d20134612521e995c72e4fa06ed791dd3 (diff)
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Merge pull request #1420 from YosysHQ/eddie/pr1363
Add tests for Xilinx architecture (contd)
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