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author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:51:32 +0200 |
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committer | GitHub <noreply@github.com> | 2019-10-18 10:51:32 +0200 |
commit | e0a67fce12647b4db7125d33264847c0a3781105 (patch) | |
tree | 38f3dc5651aa6bab8afb3217a90a7c0350ef23ae /techlibs/easic | |
parent | 0d037bf9d8d866239de15d72dc8c5acd7ab5e5cf (diff) | |
parent | e6ad714d20134612521e995c72e4fa06ed791dd3 (diff) | |
download | yosys-e0a67fce12647b4db7125d33264847c0a3781105.tar.gz yosys-e0a67fce12647b4db7125d33264847c0a3781105.tar.bz2 yosys-e0a67fce12647b4db7125d33264847c0a3781105.zip |
Merge pull request #1420 from YosysHQ/eddie/pr1363
Add tests for Xilinx architecture (contd)
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