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authorRobert Ou <rqou@robertou.com>2017-06-24 06:59:20 -0700
committerRobert Ou <rqou@robertou.com>2017-06-24 07:22:56 -0700
commit6e0fb889fafc58d40ef83e61520f68f6767f0c91 (patch)
treedfdaab4ee59f78f754e53422147d6c66238a7c80 /techlibs/coolrunner2
parent8f8baccfde62d238025024eb1060ae0aba4c77e3 (diff)
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coolrunner2: Initial commit
Diffstat (limited to 'techlibs/coolrunner2')
-rw-r--r--techlibs/coolrunner2/Makefile.inc4
-rw-r--r--techlibs/coolrunner2/cells_sim.v41
-rw-r--r--techlibs/coolrunner2/synth_coolrunner2.cpp178
3 files changed, 223 insertions, 0 deletions
diff --git a/techlibs/coolrunner2/Makefile.inc b/techlibs/coolrunner2/Makefile.inc
new file mode 100644
index 000000000..516238330
--- /dev/null
+++ b/techlibs/coolrunner2/Makefile.inc
@@ -0,0 +1,4 @@
+
+OBJS += techlibs/coolrunner2/synth_coolrunner2.o
+
+$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v))
diff --git a/techlibs/coolrunner2/cells_sim.v b/techlibs/coolrunner2/cells_sim.v
new file mode 100644
index 000000000..328e7504d
--- /dev/null
+++ b/techlibs/coolrunner2/cells_sim.v
@@ -0,0 +1,41 @@
+module IBUF(input I, output O);
+ assign O = I;
+endmodule
+
+module IOBUFE(input I, input E, output O, inout IO);
+ assign O = IO;
+ assign IO = E ? I : 1'bz;
+endmodule
+
+module ANDTERM(IN, OUT);
+ parameter WIDTH = 0;
+
+ input [(WIDTH*2)-1:0] IN;
+ output reg OUT;
+
+ integer i;
+
+ always @(*) begin
+ OUT = 1;
+ for (i = 0; i < WIDTH; i=i+1) begin
+ OUT = OUT & ~IN[i * 2 + 0];
+ OUT = OUT & IN[i * 2 + 1];
+ end
+ end
+endmodule
+
+module ORTERM(IN, OUT);
+ parameter WIDTH = 0;
+
+ input [WIDTH-1:0] IN;
+ output reg OUT;
+
+ integer i;
+
+ always @(*) begin
+ OUT = 0;
+ for (i = 0; i < WIDTH; i=i+1) begin
+ OUT = OUT | IN[i];
+ end
+ end
+endmodule
diff --git a/techlibs/coolrunner2/synth_coolrunner2.cpp b/techlibs/coolrunner2/synth_coolrunner2.cpp
new file mode 100644
index 000000000..cc6f6401d
--- /dev/null
+++ b/techlibs/coolrunner2/synth_coolrunner2.cpp
@@ -0,0 +1,178 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2017 Robert Ou <rqou@robertou.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthCoolrunner2Pass : public ScriptPass
+{
+ SynthCoolrunner2Pass() : ScriptPass("synth_coolrunner2", "synthesis for Xilinx Coolrunner-II CPLDs") { }
+
+ virtual void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" synth_coolrunner2 [options]\n");
+ log("\n");
+ log("This command runs synthesis for Coolrunner-II CPLDs. This work is experimental.\n");
+ log("It is intended to be used with https://github.com/azonenberg/openfpga as the\n");
+ log("place-and-route.\n");
+ log("\n");
+ log(" -top <module>\n");
+ log(" use the specified module as top module (default='top')\n");
+ log("\n");
+ log(" -json <file>\n");
+ log(" write the design to the specified JSON file. writing of an output file\n");
+ log(" is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -run <from_label>:<to_label>\n");
+ log(" only run the commands between the labels (see below). an empty\n");
+ log(" from label is synonymous to 'begin', and empty to label is\n");
+ log(" synonymous to the end of the command list.\n");
+ log("\n");
+ log(" -noflatten\n");
+ log(" do not flatten design before synthesis\n");
+ log("\n");
+ log(" -retime\n");
+ log(" run 'abc' with -dff option\n");
+ log("\n");
+ log("\n");
+ log("The following commands are executed by this synthesis command:\n");
+ help_script();
+ log("\n");
+ }
+
+ string top_opt, json_file;
+ bool flatten, retime;
+
+ virtual void clear_flags() YS_OVERRIDE
+ {
+ top_opt = "-auto-top";
+ json_file = "";
+ flatten = true;
+ retime = false;
+ }
+
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ string run_from, run_to;
+ clear_flags();
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-top" && argidx+1 < args.size()) {
+ top_opt = "-top " + args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-json" && argidx+1 < args.size()) {
+ json_file = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-run" && argidx+1 < args.size()) {
+ size_t pos = args[argidx+1].find(':');
+ if (pos == std::string::npos)
+ break;
+ run_from = args[++argidx].substr(0, pos);
+ run_to = args[argidx].substr(pos+1);
+ continue;
+ }
+ if (args[argidx] == "-noflatten") {
+ flatten = false;
+ continue;
+ }
+ if (args[argidx] == "-retime") {
+ retime = true;
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ if (!design->full_selection())
+ log_cmd_error("This comannd only operates on fully selected designs!\n");
+
+ log_header(design, "Executing SYNTH_COOLRUNNER2 pass.\n");
+ log_push();
+
+ run_script(design, run_from, run_to);
+
+ log_pop();
+ }
+
+ virtual void script() YS_OVERRIDE
+ {
+ if (check_label("begin"))
+ {
+ run("read_verilog -lib +/coolrunner2/cells_sim.v");
+ run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+ }
+
+ if (flatten && check_label("flatten", "(unless -noflatten)"))
+ {
+ run("proc");
+ run("flatten");
+ run("tribuf -logic");
+ }
+
+ if (check_label("coarse"))
+ {
+ run("synth -run coarse");
+ }
+
+ if (check_label("fine"))
+ {
+ run("opt -fast -full");
+ run("techmap");
+ }
+
+ if (check_label("map_pla"))
+ {
+ run("abc -sop -I 40 -P 56");
+ run("opt -fast");
+ }
+
+ if (check_label("map_cells"))
+ {
+ run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO");
+ }
+
+ if (check_label("check"))
+ {
+ run("hierarchy -check");
+ run("stat");
+ run("check -noinit");
+ }
+
+ if (check_label("json"))
+ {
+ if (!json_file.empty() || help_mode)
+ run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
+ }
+
+ log_pop();
+ }
+} SynthCoolrunner2Pass;
+
+PRIVATE_NAMESPACE_END