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authorRobert Ou <rqou@robertou.com>2017-08-30 16:38:04 -0700
committerAndrew Zonenberg <azonenberg@drawersteak.com>2017-09-01 07:21:51 -0700
commit6775177171e70c64292a78a5d860d7b82d5c64b9 (patch)
treeefee51b13901f741f16e1fec5e918ad6f0eab27e /techlibs/coolrunner2
parent7f08be430422c5fffc93cf0315e1894880b32b5b (diff)
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coolrunner2: Initial fixes for special p-terms
Certain signals can only be controlled by a product term and not a sum-of-products. Do the initial work for fixing this.
Diffstat (limited to 'techlibs/coolrunner2')
-rw-r--r--techlibs/coolrunner2/coolrunner2_sop.cc78
-rw-r--r--techlibs/coolrunner2/synth_coolrunner2.cc4
2 files changed, 81 insertions, 1 deletions
diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc
index 2d3961ee5..d526f8036 100644
--- a/techlibs/coolrunner2/coolrunner2_sop.cc
+++ b/techlibs/coolrunner2/coolrunner2_sop.cc
@@ -55,6 +55,35 @@ struct Coolrunner2SopPass : public Pass {
}
}
+ // Find wires that need to become special product terms
+ dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_no_inv;
+ dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_inv;
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
+ cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
+ cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE" ||
+ cell->type == "\\LDCP" || cell->type == "\\LDCP_N")
+ {
+ if (cell->hasPort("\\PRE"))
+ special_pterms_no_inv[sigmap(cell->getPort("\\PRE")[0])].insert(
+ tuple<Cell*, const char *>(cell, "\\PRE"));
+ if (cell->hasPort("\\CLR"))
+ special_pterms_no_inv[sigmap(cell->getPort("\\CLR")[0])].insert(
+ tuple<Cell*, const char *>(cell, "\\PRE"));
+ if (cell->hasPort("\\CE"))
+ special_pterms_no_inv[sigmap(cell->getPort("\\CE")[0])].insert(
+ tuple<Cell*, const char *>(cell, "\\PRE"));
+
+ if (cell->hasPort("\\C"))
+ special_pterms_inv[sigmap(cell->getPort("\\C")[0])].insert(
+ tuple<Cell*, const char *>(cell, "\\PRE"));
+ if (cell->hasPort("\\G"))
+ special_pterms_inv[sigmap(cell->getPort("\\G")[0])].insert(
+ tuple<Cell*, const char *>(cell, "\\PRE"));
+ }
+ }
+
// Process $sop cells
for (auto cell : module->selected_cells())
{
@@ -80,6 +109,16 @@ struct Coolrunner2SopPass : public Pass {
cells_to_remove.insert(std::get<1>(not_cell));
}
+ // Check for special P-term usage
+ bool is_special_pterm = false;
+ bool special_pterm_can_invert = false;
+ if (special_pterms_no_inv.count(sop_output) || special_pterms_inv.count(sop_output))
+ {
+ is_special_pterm = true;
+ if (!special_pterms_no_inv.count(sop_output))
+ special_pterm_can_invert = true;
+ }
+
// Construct AND cells
pool<SigBit> intermed_wires;
for (int i = 0; i < sop_depth; i++) {
@@ -118,6 +157,40 @@ struct Coolrunner2SopPass : public Pass {
xor_cell->setParam("\\INVERT_OUT", has_invert);
xor_cell->setPort("\\IN_PTC", *intermed_wires.begin());
xor_cell->setPort("\\OUT", sop_output);
+
+ // Special P-term handling
+ if (is_special_pterm)
+ {
+ if (!has_invert)
+ {
+ // Can connect the P-term directly to the special term sinks
+ for (auto x : special_pterms_inv[sop_output]) {
+ log("%s %s", std::get<0>(x)->name.c_str(), std::get<1>(x).c_str());
+ std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
+ }
+ for (auto x : special_pterms_no_inv[sop_output]) {
+ log("%s %s", std::get<0>(x)->name.c_str(), std::get<1>(x).c_str());
+ std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
+ }
+ }
+ else
+ {
+ if (special_pterm_can_invert)
+ {
+ log_assert(special_pterms_no_inv.count(sop_output) == 0);
+
+ // XXX TODO
+ log_assert(!"not implemented yet");
+ }
+ else
+ {
+ // Need to construct a set of feed-through terms
+
+ // XXX TODO
+ log_assert(!"not implemented yet");
+ }
+ }
+ }
}
else
{
@@ -135,6 +208,11 @@ struct Coolrunner2SopPass : public Pass {
xor_cell->setParam("\\INVERT_OUT", has_invert);
xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire);
xor_cell->setPort("\\OUT", sop_output);
+
+ if (is_special_pterm)
+ {
+ // Need to construct a set of feed-through terms
+ }
}
// Finally, remove the $sop cell
diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc
index fa7d9ac78..562cce460 100644
--- a/techlibs/coolrunner2/synth_coolrunner2.cc
+++ b/techlibs/coolrunner2/synth_coolrunner2.cc
@@ -152,7 +152,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
if (check_label("map_pla"))
{
run("abc -sop -I 40 -P 56");
- run("coolrunner2_sop");
+ run("clean");
}
if (check_label("map_cells"))
@@ -162,7 +162,9 @@ struct SynthCoolrunner2Pass : public ScriptPass
run("dffinit -ff FDCP_N Q INIT");
run("dffinit -ff LDCP Q INIT");
run("dffinit -ff LDCP_N Q INIT");
+ run("coolrunner2_sop");
run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO");
+ run("clean");
}
if (check_label("check"))