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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-15 00:20:05 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-15 00:20:05 +0100 |
| commit | ec05242c27754224c8dd5d8c60828a0b43ef8f4c (patch) | |
| tree | a9cf51cde1ec6bafe2fe178c9bb6d69ac03a15da /techlibs/common | |
| parent | c6ae9ebb7997548fdf7445f9fda64dc97f8e92f8 (diff) | |
| download | yosys-ec05242c27754224c8dd5d8c60828a0b43ef8f4c.tar.gz yosys-ec05242c27754224c8dd5d8c60828a0b43ef8f4c.tar.bz2 yosys-ec05242c27754224c8dd5d8c60828a0b43ef8f4c.zip | |
Smaller default parameters in $mem simlib model
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/simlib.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index ee024051b..bc343c62d 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1539,9 +1539,9 @@ endmodule module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); parameter MEMID = ""; -parameter SIZE = 256; +parameter SIZE = 4; parameter OFFSET = 0; -parameter ABITS = 8; +parameter ABITS = 2; parameter WIDTH = 8; parameter signed INIT = 1'bx; |