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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-02 22:45:26 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-02 22:57:08 +0100 |
| commit | 90f4017703a275c1a32cb347e4b60bd43873bbce (patch) | |
| tree | b9f79c5fafc9f421863ade432d556ef1351029b3 /techlibs/common | |
| parent | 1dca7ae486edd47f786b07dba6a672b45ed9a4a5 (diff) | |
| download | yosys-90f4017703a275c1a32cb347e4b60bd43873bbce.tar.gz yosys-90f4017703a275c1a32cb347e4b60bd43873bbce.tar.bz2 yosys-90f4017703a275c1a32cb347e4b60bd43873bbce.zip | |
Added proper clkpol support to memory_bram
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/simlib.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index ca4b1d36c..4680e209a 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1539,7 +1539,7 @@ function port_active; end endfunction -always @* begin +always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin for (i = 0; i < RD_PORTS; i = i+1) begin if ((!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]; |