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| author | Clifford Wolf <clifford@clifford.at> | 2013-08-20 09:38:31 -0700 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-08-20 09:38:31 -0700 |
| commit | 459e8964fd5ff115c3fdd1c4487f0fe62bd46137 (patch) | |
| tree | 27eef28e2a9c52c42fb08425b3a1a9dc96874034 /techlibs/common | |
| parent | 8e31a924070ede11967cce8c3161ffc79847932d (diff) | |
| parent | a99c22415783f5c829be5fd2ba77246b15a2734b (diff) | |
| download | yosys-459e8964fd5ff115c3fdd1c4487f0fe62bd46137.tar.gz yosys-459e8964fd5ff115c3fdd1c4487f0fe62bd46137.tar.bz2 yosys-459e8964fd5ff115c3fdd1c4487f0fe62bd46137.zip | |
Merge pull request #9 from hansiglaser/master
Added support for include directories with the new '-I' argument of the 'read_verilog' command
Diffstat (limited to 'techlibs/common')
0 files changed, 0 insertions, 0 deletions