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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 12:18:32 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 12:18:32 -0700 |
| commit | 32eef26ee277b79736e135a8800625543dd6080a (patch) | |
| tree | 28cd6d5af904ddd2ec2772e2bd1d2378215c1dc7 /techlibs/common | |
| parent | fe58790f3789a79b867660031d7e3e28cb3fff20 (diff) | |
| parent | c499dc3e73390c3bc9bf8045f2e4cad963c1fbad (diff) | |
| download | yosys-32eef26ee277b79736e135a8800625543dd6080a.tar.gz yosys-32eef26ee277b79736e135a8800625543dd6080a.tar.bz2 yosys-32eef26ee277b79736e135a8800625543dd6080a.zip | |
Merge remote-tracking branch 'origin/clifford/async2synclatch' into Sergey/tests_ice40
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/synth.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 555de9fba..a176357a7 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -175,7 +175,7 @@ struct SynthPass : public ScriptPass log_cmd_error("This command only operates on fully selected designs!\n"); if (abc == "abc9" && !lut) - log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)"); + log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)\n"); log_header(design, "Executing SYNTH pass.\n"); log_push(); |