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| author | N. Engelhardt <nak@symbioticeda.com> | 2020-03-30 13:51:12 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-30 13:51:12 +0200 |
| commit | 2c847e7efec5e940331a94580fad99375ce73c6f (patch) | |
| tree | c87b514d072beb687287ae0432e57964bf0999b9 /techlibs/common | |
| parent | 1dbc70172830c57cda22e4bc82d2db57a2067203 (diff) | |
| parent | 044ca9dde409e3c91542fe95513d6641110f8462 (diff) | |
| download | yosys-2c847e7efec5e940331a94580fad99375ce73c6f.tar.gz yosys-2c847e7efec5e940331a94580fad99375ce73c6f.tar.bz2 yosys-2c847e7efec5e940331a94580fad99375ce73c6f.zip | |
Merge pull request #1778 from rswarbrick/sv-defines
Add support for SystemVerilog-style `define to Verilog frontend
Diffstat (limited to 'techlibs/common')
0 files changed, 0 insertions, 0 deletions