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author | Ahmed Irfan <irfan@ubuntu.(none)> | 2014-01-18 17:29:55 +0100 |
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committer | Ahmed Irfan <irfan@ubuntu.(none)> | 2014-01-18 17:29:55 +0100 |
commit | da8af915522bb8cf47f19f901a8210ff3e2b6118 (patch) | |
tree | da4efbcf700f40024122effa7897be8f3b8acbb8 /techlibs/common/simlib.v | |
parent | 9a689f33a56d4b351bab021989f79e9b19500c62 (diff) | |
parent | bef17eeb109dd2dc4eaba6eb808a0172c0c53265 (diff) | |
download | yosys-da8af915522bb8cf47f19f901a8210ff3e2b6118.tar.gz yosys-da8af915522bb8cf47f19f901a8210ff3e2b6118.tar.bz2 yosys-da8af915522bb8cf47f19f901a8210ff3e2b6118.zip |
pmux2mux
Diffstat (limited to 'techlibs/common/simlib.v')
-rw-r--r-- | techlibs/common/simlib.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 034244ca6..f3d652f0e 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -55,6 +55,28 @@ endmodule // -------------------------------------------------------- +module \$bu0 (A, Y); + +parameter A_SIGNED = 0; +parameter A_WIDTH = 0; +parameter Y_WIDTH = 0; + +`INPUT_A +output [Y_WIDTH-1:0] Y; + +generate + if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:A + assign Y[A_WIDTH-1:0] = A_BUF.val; + assign Y[Y_WIDTH-1:A_WIDTH] = 0; + end else begin:B + assign Y = +A_BUF.val; + end +endgenerate + +endmodule + +// -------------------------------------------------------- + module \$pos (A, Y); parameter A_SIGNED = 0; |