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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-06-30 15:31:12 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-06-30 15:32:06 +0200 |
| commit | 817ae04ee0c445efaf83e9847d4956f2dae0d857 (patch) | |
| tree | 60d300cb70d62e69e6809fc8a4f0071e3e68f79a /techlibs/common/simcells.v | |
| parent | f7fdd99e45de5330b8f0cbb183c7b6e2ccc274b7 (diff) | |
| download | yosys-817ae04ee0c445efaf83e9847d4956f2dae0d857.tar.gz yosys-817ae04ee0c445efaf83e9847d4956f2dae0d857.tar.bz2 yosys-817ae04ee0c445efaf83e9847d4956f2dae0d857.zip | |
simcells: Fix reset polarity for $_DLATCH_???_ cells.
Diffstat (limited to 'techlibs/common/simcells.v')
| -rw-r--r-- | techlibs/common/simcells.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 01b5bdfa6..27ef44232 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -2986,7 +2986,7 @@ module \$_DLATCH_NP0_ (E, R, D, Q); input E, R, D; output reg Q; always @* begin - if (R == 0) + if (R == 1) Q <= 0; else if (E == 0) Q <= D; @@ -3009,7 +3009,7 @@ module \$_DLATCH_NP1_ (E, R, D, Q); input E, R, D; output reg Q; always @* begin - if (R == 0) + if (R == 1) Q <= 1; else if (E == 0) Q <= D; @@ -3032,7 +3032,7 @@ module \$_DLATCH_PN0_ (E, R, D, Q); input E, R, D; output reg Q; always @* begin - if (R == 1) + if (R == 0) Q <= 0; else if (E == 1) Q <= D; @@ -3055,7 +3055,7 @@ module \$_DLATCH_PN1_ (E, R, D, Q); input E, R, D; output reg Q; always @* begin - if (R == 1) + if (R == 0) Q <= 1; else if (E == 1) Q <= D; |