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| author | Eddie Hung <eddie@fpgeh.com> | 2021-03-29 22:01:57 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-29 22:01:57 -0700 |
| commit | 55dc5a4e4f7335741d2155dc0183ed4e26e8ddf8 (patch) | |
| tree | ab4ab932ea29088baafcf3c71d6c5854403528d6 /techlibs/common/abc9_model.v | |
| parent | 687f381b6985d9dda7e11535628e2fafff267af5 (diff) | |
| download | yosys-55dc5a4e4f7335741d2155dc0183ed4e26e8ddf8.tar.gz yosys-55dc5a4e4f7335741d2155dc0183ed4e26e8ddf8.tar.bz2 yosys-55dc5a4e4f7335741d2155dc0183ed4e26e8ddf8.zip | |
abc9: fix SCC issues (#2694)
* xilinx: add SCC test for DSP48E1
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
* abc9 to break SCCs using $__ABC9_SCC_BREAKER module
* Add test
* abc9_ops: remove refs to (* abc9_keep *) on wires
* abc9_ops: do not bypass cells in an SCC
* Add myself to CODEOWNERS for abc9*
* Fix compile
* abc9_ops: run -prep_hier before scc
* Fix tests
* Remove bug reference pending fix
* abc9: fix for -prep_hier -dff
* xaiger: restore PI handling
* abc9_ops: -prep_xaiger sigmap
* abc9_ops: -mark_scc -> -break_scc
* abc9: eliminate hard-coded abc9.box from tests
Also tidy up
* Address review
Diffstat (limited to 'techlibs/common/abc9_model.v')
| -rw-r--r-- | techlibs/common/abc9_model.v | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/techlibs/common/abc9_model.v b/techlibs/common/abc9_model.v index 4fee60f75..570a1ec40 100644 --- a/techlibs/common/abc9_model.v +++ b/techlibs/common/abc9_model.v @@ -6,6 +6,10 @@ module $__ABC9_DELAY (input I, output O); endspecify endmodule +module $__ABC9_SCC_BREAKER (input [WIDTH-1:0] I, output [WIDTH-1:0] O); +parameter WIDTH = 0; +endmodule + (* abc9_flop, abc9_box, lib_whitebox *) module $__DFF_N__$abc9_flop (input C, D, Q, output n1); assign n1 = D; |