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author | Clifford Wolf <clifford@clifford.at> | 2015-10-13 15:40:21 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-10-13 15:41:20 +0200 |
commit | f42218682d2c7caa6caa81cb2ca48f0c3f62bb5b (patch) | |
tree | eed220c7c84c673dec27bca4c2e96d919831f8b7 /techlibs/cmos | |
parent | f13e3873212fb4338ee3dd180cb9b0cd3d134935 (diff) | |
download | yosys-f42218682d2c7caa6caa81cb2ca48f0c3f62bb5b.tar.gz yosys-f42218682d2c7caa6caa81cb2ca48f0c3f62bb5b.tar.bz2 yosys-f42218682d2c7caa6caa81cb2ca48f0c3f62bb5b.zip |
Added examples/ top-level directory
Diffstat (limited to 'techlibs/cmos')
-rw-r--r-- | techlibs/cmos/cmos_cells.lib | 55 | ||||
-rw-r--r-- | techlibs/cmos/cmos_cells.sp | 39 | ||||
-rw-r--r-- | techlibs/cmos/cmos_cells.v | 44 | ||||
-rw-r--r-- | techlibs/cmos/counter.v | 12 | ||||
-rw-r--r-- | techlibs/cmos/counter.ys | 16 | ||||
-rw-r--r-- | techlibs/cmos/testbench.sh | 7 | ||||
-rw-r--r-- | techlibs/cmos/testbench.sp | 29 |
7 files changed, 0 insertions, 202 deletions
diff --git a/techlibs/cmos/cmos_cells.lib b/techlibs/cmos/cmos_cells.lib deleted file mode 100644 index 1b0bf8457..000000000 --- a/techlibs/cmos/cmos_cells.lib +++ /dev/null @@ -1,55 +0,0 @@ -// test comment -/* test comment */ -library(demo) { - cell(BUF) { - area: 6; - pin(A) { direction: input; } - pin(Y) { direction: output; - function: "A"; } - } - cell(NOT) { - area: 3; - pin(A) { direction: input; } - pin(Y) { direction: output; - function: "A'"; } - } - cell(NAND) { - area: 4; - pin(A) { direction: input; } - pin(B) { direction: input; } - pin(Y) { direction: output; - function: "(A*B)'"; } - } - cell(NOR) { - area: 4; - pin(A) { direction: input; } - pin(B) { direction: input; } - pin(Y) { direction: output; - function: "(A+B)'"; } - } - cell(DFF) { - area: 18; - ff(IQ, IQN) { clocked_on: C; - next_state: D; } - pin(C) { direction: input; - clock: true; } - pin(D) { direction: input; } - pin(Q) { direction: output; - function: "IQ"; } - } - cell(DFFSR) { - area: 18; - ff("IQ", "IQN") { clocked_on: C; - next_state: D; - preset: S; - clear: R; } - pin(C) { direction: input; - clock: true; } - pin(D) { direction: input; } - pin(Q) { direction: output; - function: "IQ"; } - pin(S) { direction: input; } - pin(R) { direction: input; } - ; // empty statement - } -} diff --git a/techlibs/cmos/cmos_cells.sp b/techlibs/cmos/cmos_cells.sp deleted file mode 100644 index 673b20d08..000000000 --- a/techlibs/cmos/cmos_cells.sp +++ /dev/null @@ -1,39 +0,0 @@ - -.SUBCKT BUF A Y -X1 A B NOT -X2 B Y NOT -.ENDS NOT - -.SUBCKT NOT A Y -M1 Y A Vdd Vdd cmosp L=1u W=10u -M2 Y A Vss Vss cmosn L=1u W=10u -.ENDS NOT - -.SUBCKT NAND A B Y -M1 Y A Vdd Vdd cmosp L=1u W=10u -M2 Y B Vdd Vdd cmosp L=1u W=10u -M3 Y A M34 Vss cmosn L=1u W=10u -M4 M34 B Vss Vss cmosn L=1u W=10u -.ENDS NAND - -.SUBCKT NOR A B Y -M1 Y A M12 Vdd cmosp L=1u W=10u -M2 M12 B Vdd Vdd cmosp L=1u W=10u -M3 Y A Vss Vss cmosn L=1u W=10u -M4 Y B Vss Vss cmosn L=1u W=10u -.ENDS NOR - -.SUBCKT DLATCH E D Q -X1 D E S NAND -X2 nD E R NAND -X3 S nQ Q NAND -X4 Q R nQ NAND -X5 D nD NOT -.ENDS DLATCH - -.SUBCKT DFF C D Q -X1 nC D t DLATCH -X2 C t Q DLATCH -X3 C nC NOT -.ENDS DFF - diff --git a/techlibs/cmos/cmos_cells.v b/techlibs/cmos/cmos_cells.v deleted file mode 100644 index 27278facb..000000000 --- a/techlibs/cmos/cmos_cells.v +++ /dev/null @@ -1,44 +0,0 @@ - -module BUF(A, Y); -input A; -output Y; -assign Y = A; -endmodule - -module NOT(A, Y); -input A; -output Y; -assign Y = ~A; -endmodule - -module NAND(A, B, Y); -input A, B; -output Y; -assign Y = ~(A & B); -endmodule - -module NOR(A, B, Y); -input A, B; -output Y; -assign Y = ~(A | B); -endmodule - -module DFF(C, D, Q); -input C, D; -output reg Q; -always @(posedge C) - Q <= D; -endmodule - -module DFFSR(C, D, Q, S, R); -input C, D, S, R; -output reg Q; -always @(posedge C, posedge S, posedge R) - if (S) - Q <= 1'b1; - else if (R) - Q <= 1'b0; - else - Q <= D; -endmodule - diff --git a/techlibs/cmos/counter.v b/techlibs/cmos/counter.v deleted file mode 100644 index f21658724..000000000 --- a/techlibs/cmos/counter.v +++ /dev/null @@ -1,12 +0,0 @@ -module counter (clk, rst, en, count); - - input clk, rst, en; - output reg [2:0] count; - - always @(posedge clk) - if (rst) - count <= 3'd0; - else if (en) - count <= count + 3'd1; - -endmodule diff --git a/techlibs/cmos/counter.ys b/techlibs/cmos/counter.ys deleted file mode 100644 index a784f3465..000000000 --- a/techlibs/cmos/counter.ys +++ /dev/null @@ -1,16 +0,0 @@ - -read_verilog counter.v -read_verilog -lib cmos_cells.v - -proc;; memory;; techmap;; - -dfflibmap -liberty cmos_cells.lib -abc -liberty cmos_cells.lib;; - -# http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib -# dfflibmap -liberty osu025_stdcells.lib -# abc -liberty osu025_stdcells.lib;; - -write_verilog synth.v -write_spice synth.sp - diff --git a/techlibs/cmos/testbench.sh b/techlibs/cmos/testbench.sh deleted file mode 100644 index 061704b64..000000000 --- a/techlibs/cmos/testbench.sh +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/bash - -set -ex - -../../yosys counter.ys -ngspice testbench.sp - diff --git a/techlibs/cmos/testbench.sp b/techlibs/cmos/testbench.sp deleted file mode 100644 index 95d2f67cd..000000000 --- a/techlibs/cmos/testbench.sp +++ /dev/null @@ -1,29 +0,0 @@ - -* supply voltages -.global Vss Vdd -Vss Vss 0 DC 0 -Vdd Vdd 0 DC 3 - -* simple transistor model -.MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7 -.MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8 - -* load design and library -.include synth.sp -.include cmos_cells.sp - -* input signals -Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2) -Vrst rst 0 PULSE(0 3 0.5 0.1 0.1 2.9 40) -Ven en 0 PULSE(0 3 0.5 0.1 0.1 5.9 8) - -Xuut clk rst en out0 out1 out2 COUNTER - -.tran 0.01 50 - -.control -run -plot v(clk) v(rst)+5 v(en)+10 v(out0)+20 v(out1)+25 v(out2)+30 -.endc - -.end |