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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-03 12:30:22 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-03 12:32:05 -0800 |
| commit | e62eb02c1dd3074e58c9be64b8bb3b13b8d9a1ea (patch) | |
| tree | 7e68756aaddc58d2f7e298abd70d0807aac48de0 /techlibs/anlogic/synth_anlogic.cc | |
| parent | dedea5a58d00b97180a9e0a2645f1018add00a36 (diff) | |
| download | yosys-e62eb02c1dd3074e58c9be64b8bb3b13b8d9a1ea.tar.gz yosys-e62eb02c1dd3074e58c9be64b8bb3b13b8d9a1ea.tar.bz2 yosys-e62eb02c1dd3074e58c9be64b8bb3b13b8d9a1ea.zip | |
Restore write_xaiger's holes_mode since port_id order causes QoR
regressions inside abc9
Diffstat (limited to 'techlibs/anlogic/synth_anlogic.cc')
0 files changed, 0 insertions, 0 deletions