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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-02 16:28:18 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-01-02 16:28:18 +0100 |
| commit | 56ca1e6afc66542666e73356cbe62f6ca64215a7 (patch) | |
| tree | ef73ada0584e9f8c0656e91fe6c16507600632dd /techlibs/anlogic/synth_anlogic.cc | |
| parent | b236faffa1f4e80f8af191469c89f582d3e0c324 (diff) | |
| parent | 90d00182cfe358438d777f2ca7abacb4c6a2733c (diff) | |
| download | yosys-56ca1e6afc66542666e73356cbe62f6ca64215a7.tar.gz yosys-56ca1e6afc66542666e73356cbe62f6ca64215a7.tar.bz2 yosys-56ca1e6afc66542666e73356cbe62f6ca64215a7.zip | |
Merge pull request #755 from Icenowy/anlogic-dram-init
anlogic: implement DRAM initialization
Diffstat (limited to 'techlibs/anlogic/synth_anlogic.cc')
| -rw-r--r-- | techlibs/anlogic/synth_anlogic.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index fab199fd7..620bf3965 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -154,6 +154,7 @@ struct SynthAnlogicPass : public ScriptPass { run("memory_bram -rules +/anlogic/drams.txt"); run("techmap -map +/anlogic/drams_map.v"); + run("anlogic_determine_init"); } if (check_label("fine")) |