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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-02-27 09:57:10 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-18 17:32:56 +0200 |
| commit | f4d1426229e0843d55a7ac2a10760acecf9c6710 (patch) | |
| tree | 7912276260474807286ed98c7516f05a7dba0c28 /techlibs/anlogic/lutrams.txt | |
| parent | d7dc2313b915d3c316630104a86eb754744fdd57 (diff) | |
| download | yosys-f4d1426229e0843d55a7ac2a10760acecf9c6710.tar.gz yosys-f4d1426229e0843d55a7ac2a10760acecf9c6710.tar.bz2 yosys-f4d1426229e0843d55a7ac2a10760acecf9c6710.zip | |
anlogic: Use `memory_libmap` pass.
Diffstat (limited to 'techlibs/anlogic/lutrams.txt')
| -rw-r--r-- | techlibs/anlogic/lutrams.txt | 28 |
1 files changed, 12 insertions, 16 deletions
diff --git a/techlibs/anlogic/lutrams.txt b/techlibs/anlogic/lutrams.txt index 4e903c0a2..ef6fec24e 100644 --- a/techlibs/anlogic/lutrams.txt +++ b/techlibs/anlogic/lutrams.txt @@ -1,16 +1,12 @@ -bram $__ANLOGIC_DRAM16X4 - init 1 - abits 4 - dbits 4 - groups 2 - ports 1 1 - wrmode 0 1 - enable 0 1 - transp 0 0 - clocks 0 1 - clkpol 0 1 -endbram - -match $__ANLOGIC_DRAM16X4 - make_outreg -endmatch +ram distributed $__ANLOGIC_DRAM16X4_ { + abits 4; + width 4; + cost 4; + init no_undef; + prune_rom; + port sw "W" { + clock posedge; + } + port ar "R" { + } +} |