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authorEddie Hung <eddie@fpgeh.com>2019-08-20 11:57:52 -0700
committerEddie Hung <eddie@fpgeh.com>2019-08-20 11:57:52 -0700
commitd9fe4cccbf3cc03fa57b177fd13c6e900a2134f7 (patch)
treeaceb37b755f6b112e754bbdd50f0a4a6a6ee111d /techlibs/anlogic/anlogic_determine_init.cc
parent297a9802122817e143b1e4b87fd0d4e357606a72 (diff)
parent3f4886e7a3ff14578b9c6d614efd360478e5886e (diff)
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Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
Diffstat (limited to 'techlibs/anlogic/anlogic_determine_init.cc')
-rw-r--r--techlibs/anlogic/anlogic_determine_init.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/anlogic/anlogic_determine_init.cc b/techlibs/anlogic/anlogic_determine_init.cc
index 34b1d4f8a..c4089dac2 100644
--- a/techlibs/anlogic/anlogic_determine_init.cc
+++ b/techlibs/anlogic/anlogic_determine_init.cc
@@ -50,7 +50,7 @@ struct AnlogicDetermineInitPass : public Pass {
extra_args(args, args.size(), design);
- size_t cnt = 0;
+ int cnt = 0;
for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())
@@ -65,7 +65,7 @@ struct AnlogicDetermineInitPass : public Pass {
}
}
}
- log_header(design, "Updated %lu cells with determined init value.\n", cnt);
+ log_header(design, "Updated %d cells with determined init value.\n", cnt);
}
} AnlogicDetermineInitPass;