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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-29 09:16:09 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-29 09:16:09 -0700 |
| commit | b4f38cca77a78884ce215190935af78cae92c4db (patch) | |
| tree | 7a2f88af3d923113c2a02eaa23d663b474b21cd2 /techlibs/anlogic/anlogic_determine_init.cc | |
| parent | ccf759864ad0070faa9e4cbe1609389b4885f7c0 (diff) | |
| parent | 92694ea3a997cc6d081b6896c213d308adb466d5 (diff) | |
| download | yosys-b4f38cca77a78884ce215190935af78cae92c4db.tar.gz yosys-b4f38cca77a78884ce215190935af78cae92c4db.tar.bz2 yosys-b4f38cca77a78884ce215190935af78cae92c4db.zip | |
Merge pull request #1228 from YosysHQ/dave/yy_buf_size
verilog_lexer: Increase YY_BUF_SIZE to 65536
Diffstat (limited to 'techlibs/anlogic/anlogic_determine_init.cc')
0 files changed, 0 insertions, 0 deletions