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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:26:55 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:26:55 -0700 |
commit | d672b1ddecf30cc7fd005ce7a06ab6c2d3dca1a5 (patch) | |
tree | 46140158ab5a760da9280900e00240e5a1e6dca9 /techlibs/anlogic/Makefile.inc | |
parent | c7af71ecde65ad310e487a296b957678412fca74 (diff) | |
parent | 509c353fe981c95ca667a637bf2b47477962a60b (diff) | |
download | yosys-d672b1ddecf30cc7fd005ce7a06ab6c2d3dca1a5.tar.gz yosys-d672b1ddecf30cc7fd005ce7a06ab6c2d3dca1a5.tar.bz2 yosys-d672b1ddecf30cc7fd005ce7a06ab6c2d3dca1a5.zip |
Merge remote-tracking branch 'origin/master' into xaig_arrival
Diffstat (limited to 'techlibs/anlogic/Makefile.inc')
-rw-r--r-- | techlibs/anlogic/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc index 67cf9cf10..9426b5ca5 100644 --- a/techlibs/anlogic/Makefile.inc +++ b/techlibs/anlogic/Makefile.inc @@ -1,7 +1,7 @@ OBJS += techlibs/anlogic/synth_anlogic.o OBJS += techlibs/anlogic/anlogic_eqn.o -OBJS += techlibs/anlogic/anlogic_determine_init.o +OBJS += techlibs/anlogic/anlogic_fixcarry.o $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v)) |