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| author | Icenowy Zheng <icenowy@aosc.io> | 2018-12-19 10:18:47 +0800 |
|---|---|---|
| committer | Icenowy Zheng <icenowy@aosc.io> | 2018-12-20 07:56:15 +0800 |
| commit | 90d00182cfe358438d777f2ca7abacb4c6a2733c (patch) | |
| tree | 5af285a46aa934a6b8b3a1aa316a26983a1054f4 /techlibs/anlogic/Makefile.inc | |
| parent | 93d44bb9a613b46a80642b8ce71295db18fadbc5 (diff) | |
| download | yosys-90d00182cfe358438d777f2ca7abacb4c6a2733c.tar.gz yosys-90d00182cfe358438d777f2ca7abacb4c6a2733c.tar.bz2 yosys-90d00182cfe358438d777f2ca7abacb4c6a2733c.zip | |
anlogic: implement DRAM initialization
As the TD tool doesn't accept the DRAM cell to contain unknown values in
the initial value, the initialzation support of DRAM is previously
skipped.
Now add the support by add a new pass to determine unknown values in the
initial value.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Diffstat (limited to 'techlibs/anlogic/Makefile.inc')
| -rw-r--r-- | techlibs/anlogic/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc index f37b5e7e9..67cf9cf10 100644 --- a/techlibs/anlogic/Makefile.inc +++ b/techlibs/anlogic/Makefile.inc @@ -1,6 +1,7 @@ OBJS += techlibs/anlogic/synth_anlogic.o OBJS += techlibs/anlogic/anlogic_eqn.o +OBJS += techlibs/anlogic/anlogic_determine_init.o $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v)) @@ -8,3 +9,4 @@ $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/dram_init_16x4.vh)) |