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| author | Miodrag Milanovic <mmicko@gmail.com> | 2018-12-01 18:28:54 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2018-12-01 18:28:54 +0100 |
| commit | 83bce9f59c2ae54038f1cf2938fd095e7039c38a (patch) | |
| tree | 1e5010e614646cb4262e79c90ec9e2b74dbd5be9 /techlibs/anlogic/Makefile.inc | |
| parent | 47c89d600c11aee97e325351d295781169d62978 (diff) | |
| download | yosys-83bce9f59c2ae54038f1cf2938fd095e7039c38a.tar.gz yosys-83bce9f59c2ae54038f1cf2938fd095e7039c38a.tar.bz2 yosys-83bce9f59c2ae54038f1cf2938fd095e7039c38a.zip | |
Initial support for Anlogic FPGA
Diffstat (limited to 'techlibs/anlogic/Makefile.inc')
| -rw-r--r-- | techlibs/anlogic/Makefile.inc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc new file mode 100644 index 000000000..750dced31 --- /dev/null +++ b/techlibs/anlogic/Makefile.inc @@ -0,0 +1,8 @@ + +OBJS += techlibs/anlogic/synth_anlogic.o +OBJS += techlibs/anlogic/anlogic_eqn.o + +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v)) |