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| author | whitequark <whitequark@whitequark.org> | 2020-01-01 12:30:00 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-01-01 12:30:00 +0000 |
| commit | 550310e2647c7aac1e49b79d9ff912436103062f (patch) | |
| tree | 7627eab28fcd68104522d1623108ebb478c9aa84 /techlibs/anlogic/Makefile.inc | |
| parent | 22fe931c861aa3f557327baf9d12ec57006308d9 (diff) | |
| download | yosys-550310e2647c7aac1e49b79d9ff912436103062f.tar.gz yosys-550310e2647c7aac1e49b79d9ff912436103062f.tar.bz2 yosys-550310e2647c7aac1e49b79d9ff912436103062f.zip | |
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
This commit:
* renames all remaining instances of "DRAM" (which is ambiguous)
to "LUTRAM" (which is not), finishing the work started in
the commit 698ab9be;
* renames memory rule files to brams.txt/lutrams.txt;
* adds/renames script labels map_bram/map_lutram;
* extracts where necessary script labels map_ffram and map_gates;
* adds where necessary options -nobram/-nolutram.
The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.
Per architecture:
* anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
:map_lutram, :map_ffram, :map_gates
* ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
* efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
:map_gates
* gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
rename -nodram→-nolutram (-nodram still recognized), rename
:bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
Diffstat (limited to 'techlibs/anlogic/Makefile.inc')
| -rw-r--r-- | techlibs/anlogic/Makefile.inc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc index 9426b5ca5..2d8d65e2e 100644 --- a/techlibs/anlogic/Makefile.inc +++ b/techlibs/anlogic/Makefile.inc @@ -7,6 +7,6 @@ $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v)) -$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt)) -$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v)) -$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/dram_init_16x4.vh)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams.txt)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams_map.v)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutram_init_16x4.vh)) |