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| author | Clifford Wolf <clifford@clifford.at> | 2017-04-07 09:58:54 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-04-07 09:58:54 +0200 |
| commit | 7791888703a72880679ebe8ae3bbdc63db8f00e2 (patch) | |
| tree | f474149e35f09f18cc6ff701ec03c667bd76477c /techlibs/altera_intel/Makefile.inc | |
| parent | fcb274a5644016c4090cdfbfbd795f311a7e58f5 (diff) | |
| parent | c27dcc1e47fa00cd415893c9d3f637a5d5865988 (diff) | |
| download | yosys-7791888703a72880679ebe8ae3bbdc63db8f00e2.tar.gz yosys-7791888703a72880679ebe8ae3bbdc63db8f00e2.tar.bz2 yosys-7791888703a72880679ebe8ae3bbdc63db8f00e2.zip | |
Merge pull request #337 from dh73/master
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
Diffstat (limited to 'techlibs/altera_intel/Makefile.inc')
| -rw-r--r-- | techlibs/altera_intel/Makefile.inc | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/techlibs/altera_intel/Makefile.inc b/techlibs/altera_intel/Makefile.inc new file mode 100644 index 000000000..56ee56e88 --- /dev/null +++ b/techlibs/altera_intel/Makefile.inc @@ -0,0 +1,10 @@ + +OBJS += techlibs/altera_intel/synth_intel.o + +#$(eval $(call add_share_file,share/altera_intel,techlibs/altera_intel/lpm_functions.v)) +$(eval $(call add_share_file,share/altera_intel/max10,techlibs/altera_intel/max10/cells_comb_max10.v)) +$(eval $(call add_share_file,share/altera_intel/cycloneiv,techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v)) +$(eval $(call add_share_file,share/altera_intel/max10,techlibs/altera_intel/max10/cells_map_max10.v)) +$(eval $(call add_share_file,share/altera_intel/cycloneiv,techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v)) +#$(eval $(call add_share_file,share/altera_intel/max10,techlibs/altera_intel/max10/cells_arith_max10.v)) + |