Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device

4 files changed, 55 insertions, 118 deletions

diff --git a/techlibs/achronix/Makefile.inc b/techlibs/achronix/Makefile.inc
index affe0334a..994cf0015 100755
--- a/techlibs/achronix/Makefile.inc
+++ b/techlibs/achronix/Makefile.inc
@@ -1,5 +1,5 @@
 
-OBJS += techlibs/achronix/synth_speedster.o
+OBJS += techlibs/achronix/synth_achronix.o
 
 $(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_sim.v))
 $(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map.v))
diff --git a/techlibs/achronix/speedster22i/cells_map.v b/techlibs/achronix/speedster22i/cells_map.v
index 90f87826d..95f5d59c5 100755
--- a/techlibs/achronix/speedster22i/cells_map.v
+++ b/techlibs/achronix/speedster22i/cells_map.v
@@ -16,53 +16,25 @@
  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
  */
-// Normal mode DFF negedge clk, negedge reset
-module  \$_DFF_N_ (input D, C, output Q);
-   parameter WYSIWYG="TRUE";
-   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-// Normal mode DFF
-module  \$_DFF_P_ (input D, C, output Q);
-   parameter WYSIWYG="TRUE";
-   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-
-// Async Active Low Reset DFF
-module  \$_DFF_PN0_ (input D, C, R, output Q);
-   parameter WYSIWYG="TRUE";
-   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-// Async Active High Reset DFF
-module  \$_DFF_PP0_ (input D, C, R, output Q);
-   parameter WYSIWYG="TRUE";
-   wire R_i = ~ R;
-   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-// Async Active Low Reset DFF
-module  \$_DFF_PN0_ (input D, C, R, output Q);
-   parameter WYSIWYG="TRUE";
-   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-/* */
-module  \$__DFFE_PP0 (input D, C, E, R, output Q);
-   parameter WYSIWYG="TRUE";
-   wire E_i = ~ E;
-   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
-endmodule
+// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
+// > Achronix eFPGA technology mapping. User must first simulate the generated \
+// > netlist before going to test it on board/custom chip.
 
+// > Input/Output buffers <
 // Input buffer map
 module \$__inpad (input I, output O);
     PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
 endmodule
-
 // Output buffer map
 module \$__outpad (input I, output O);
     PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
 endmodule
+// > end buffers <
 
+// > Look-Up table <
+// > VT: I still think Achronix folks would have choosen a better \
+// >     logic architecture.
 // LUT Map
-/* 0 -> datac
-   1 -> cin */
 module \$lut (A, Y);
    parameter WIDTH  = 0;
    parameter LUT    = 0;
@@ -70,19 +42,31 @@ module \$lut (A, Y);
    output 	     Y;
    generate
       if (WIDTH == 1) begin
-	   assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
+	   // VT: This is not consistent and ACE will complain: assign Y = ~A[0];
+         LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ 
+           (.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0));
       end else
       if (WIDTH == 2) begin
-              LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0),.din3(1'b0));
+              LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ 
+                (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0));
       end else
       if(WIDTH == 3) begin
-	      LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]),.din3(1'b0));
+	      LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_ 
+                (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0));
       end else
       if(WIDTH == 4) begin
-             LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
+             LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_ 
+               (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
       end else
 	   wire _TECHMAP_FAIL_ = 1;
    endgenerate
-endmodule //
+endmodule 
+// > end LUT <
 
+// > Flops <
+// DFF flop
+module  \$_DFF_P_ (input D, C, output Q);
+   DFF _TECHMAP_REPLACE_ 
+     (.q(Q), .d(D), .ck(C));
+endmodule 
 
diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v
index 24c57c41a..da23fed7e 100755
--- a/techlibs/achronix/speedster22i/cells_sim.v
+++ b/techlibs/achronix/speedster22i/cells_sim.v
@@ -16,50 +16,31 @@
  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
  */
+// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
+// > Achronix eFPGA technology sim models. User must first simulate the generated \
+// > netlist before going to test it on board/custom chip.
+// > Changelog: 1) Removed unused VCC/GND modules
+// >            2) Altera comments here (?). Removed.
+// >            3) Reusing LUT sim model, removed wrong wires and parameters.
 
-module VCC (output V);
-   assign V = 1'b1;
-endmodule // VCC
-
-module GND (output G);
-   assign G = 1'b0;
-endmodule // GND
-
-/* Altera MAX10 devices Input Buffer Primitive */
 module PADIN (output padout, input padin);
    assign padout = padin;
-endmodule // fiftyfivenm_io_ibuf
+endmodule
 
-/* Altera MAX10 devices Output Buffer Primitive */
 module PADOUT (output padout, input padin, input oe);
    assign padout  = padin;
    assign oe = oe;
-endmodule // fiftyfivenm_io_obuf
+endmodule 
 
-/* Altera MAX10 4-input non-fracturable LUT Primitive */
 module LUT4 (output dout,
              input  din0, din1, din2, din3);
 
-/* Internal parameters which define the behaviour
-   of the LUT primitive.
-   lut_mask define the lut function, can be expressed in 16-digit bin or hex.
-   sum_lutc_input define the type of LUT (combinational | arithmetic).
-   dont_touch for retiming || carry options.
-   lpm_type for WYSIWYG */
-
-parameter lut_function = 16'hFFFF;
-//parameter dont_touch = "off";
-//parameter lpm_type = "fiftyfivenm_lcell_comb";
-//parameter sum_lutc_input = "datac";
-
-reg [1:0] lut_type;
-reg cout_rt;
+parameter [15:0] lut_function = 16'hFFFF;
 reg combout_rt;
 wire dataa_w;
 wire datab_w;
 wire datac_w;
 wire datad_w;
-wire cin_w;
 
 assign dataa_w = din0;
 assign datab_w = din1;
@@ -78,49 +59,21 @@ reg [1:0]   s1;
        s1 = datab ?   s2[3:2]  :   s2[1:0];
        lut_data = dataa ? s1[1] : s1[0];
   end
-
 endfunction
 
-initial begin
-    /*if (sum_lutc_input == "datac")*/ lut_type = 0;
-    /*else
-    if (sum_lutc_input == "cin")   lut_type = 1;
-    else begin
-      $error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
-      $finish();
-    end*/
-end
-
 always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
-    if (lut_type == 0) begin // logic function
-        combout_rt = lut_data(lut_function, dataa_w, datab_w,
-                            datac_w, datad_w);
-    end
-    else if (lut_type == 1) begin // arithmetic function
-        combout_rt = lut_data(lut_function, dataa_w, datab_w,
-                            cin_w, datad_w);
-    end
-    cout_rt = lut_data(lut_function, dataa_w, datab_w, cin_w, 'b0);
+   combout_rt = lut_data(lut_function, dataa_w, datab_w,
+                         datac_w, datad_w);
 end
-
 assign dout = combout_rt & 1'b1;
-//assign cout = cout_rt & 1'b1;
-
-endmodule // fiftyfivenm_lcell_comb
-
-/* Altera MAX10 D Flip-Flop Primitive */
-// TODO: Implement advanced simulation functions
-module dffeas ( output q,
-                input d, clk, clrn, prn, ena,
-		input asdata, aload, sclr, sload );
-
-parameter power_up="dontcare";
-parameter is_wysiwyg="false";
-  reg q;
-
-  always @(posedge clk)
-    q <= d;
-
+endmodule 
+
+module DFF (output q,
+            input  d, ck);
+   reg             q;
+   always @(posedge ck)
+     q <= d;
+   
 endmodule
 
 
diff --git a/techlibs/achronix/synth_speedster.cc b/techlibs/achronix/synth_achronix.cc
index 3808af6f1..7f4503070 100755
--- a/techlibs/achronix/synth_speedster.cc
+++ b/techlibs/achronix/synth_achronix.cc
@@ -25,14 +25,14 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-struct SynthIntelPass : public ScriptPass {
-  SynthIntelPass() : ScriptPass("synth_speedster", "synthesis for Acrhonix Speedster22i FPGAs.") { }
+struct SynthAchronixPass : public ScriptPass {
+  SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { }
 
   virtual void help() YS_OVERRIDE
   {
     //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
     log("\n");
-    log("    synth_speedster [options]\n");
+    log("    synth_achronix [options]\n");
     log("\n");
     log("This command runs synthesis for Achronix Speedster eFPGAs. This work is still experimental.\n");
     log("\n");
@@ -110,7 +110,7 @@ struct SynthIntelPass : public ScriptPass {
     if (!design->full_selection())
       log_cmd_error("This comannd only operates on fully selected designs!\n");
 
-    log_header(design, "Executing SYNTH_SPEEDSTER pass.\n");
+    log_header(design, "Executing SYNTH_ACHRONIX pass.\n");
     log_push();
 
     run_script(design, run_from, run_to);
@@ -146,9 +146,9 @@ struct SynthIntelPass : public ScriptPass {
         run("opt -undriven -fine");
         run("dffsr2dff");
         run("dff2dffe -direct-match $_DFF_*");
-        run("opt -full");
+        run("opt -fine");
         run("techmap -map +/techmap.v");
-        run("opt -fast");
+        run("opt -full");
         run("clean -purge");
         run("setundef -undriven -zero");
         if (retime || help_mode)
@@ -157,7 +157,7 @@ struct SynthIntelPass : public ScriptPass {
 
     if (check_label("map_luts"))
       {
-        run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+        run("abc -lut 4" + string(retime ? " -dff" : ""));
         run("clean");
       }
 
@@ -165,7 +165,7 @@ struct SynthIntelPass : public ScriptPass {
       {
         run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I");
         run("techmap -map +/achronix/speedster22i/cells_map.v");
-        run("dffinit -ff dffeas Q INIT");
+        // VT: not done yet run("dffinit -highlow -ff DFF q power_up");
         run("clean -purge");
       }
 
@@ -179,10 +179,10 @@ struct SynthIntelPass : public ScriptPass {
     if (check_label("vout"))
       {
         if (!vout_file.empty() || help_mode)
-          run(stringf("write_verilog -nodec -attr2comment -defparam -nohex -renameprefix yosys_ %s",
+          run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix syn_ %s",
                       help_mode ? "<file-name>" : vout_file.c_str()));
       }
   }
-} SynthIntelPass;
+} SynthAchronixPass;
 
 PRIVATE_NAMESPACE_END