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| author | dh73 <dh73_fpga@qq.com> | 2017-11-08 20:23:55 -0600 |
|---|---|---|
| committer | dh73 <dh73_fpga@qq.com> | 2017-11-08 20:23:55 -0600 |
| commit | 1fc061d90c45166f87d92f76b6fae1ec517be72f (patch) | |
| tree | b7c0418b904bfe2e730d6a29cadabdcfcf416496 /techlibs/achronix/Makefile.inc | |
| parent | adf17547290b403e863ed7c71960a5678c6bbfaf (diff) | |
| download | yosys-1fc061d90c45166f87d92f76b6fae1ec517be72f.tar.gz yosys-1fc061d90c45166f87d92f76b6fae1ec517be72f.tar.bz2 yosys-1fc061d90c45166f87d92f76b6fae1ec517be72f.zip | |
Organizing Speedster file names
Diffstat (limited to 'techlibs/achronix/Makefile.inc')
| -rwxr-xr-x | techlibs/achronix/Makefile.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/achronix/Makefile.inc b/techlibs/achronix/Makefile.inc index 4dfa59856..affe0334a 100755 --- a/techlibs/achronix/Makefile.inc +++ b/techlibs/achronix/Makefile.inc @@ -1,6 +1,6 @@ OBJS += techlibs/achronix/synth_speedster.o -$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_comb_speedster.v)) -$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map_speedster.v)) +$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_sim.v)) +$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map.v)) |