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| author | Clifford Wolf <clifford@clifford.at> | 2018-03-04 21:22:20 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2018-03-04 21:22:20 +0100 |
| commit | 8b7602e660b15a6a9dd7f773c3f7d7021f36659b (patch) | |
| tree | d58f95ab42dd4457bf1708e21805e99bb7fc9ac5 /techlibs/.gitignore | |
| parent | 45a6fce92c595bf406f771c97d5a1de359f465f9 (diff) | |
| download | yosys-8b7602e660b15a6a9dd7f773c3f7d7021f36659b.tar.gz yosys-8b7602e660b15a6a9dd7f773c3f7d7021f36659b.tar.bz2 yosys-8b7602e660b15a6a9dd7f773c3f7d7021f36659b.zip | |
Improve SMT2 encoding of $reduce_{and,or,bool}
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs/.gitignore')
0 files changed, 0 insertions, 0 deletions