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| author | Udi Finkelstein <github@udifink.com> | 2018-03-09 10:35:33 +0200 |
|---|---|---|
| committer | Udi Finkelstein <github@udifink.com> | 2018-03-11 23:09:34 +0200 |
| commit | 2b9c75f8e372f6886e073743d1df11bcd1c58281 (patch) | |
| tree | 756704366060541ff047db59878e059971503ec6 /techlibs/.gitignore | |
| parent | efaef82f75d8e477baf958eac39f538e6eed5b03 (diff) | |
| download | yosys-2b9c75f8e372f6886e073743d1df11bcd1c58281.tar.gz yosys-2b9c75f8e372f6886e073743d1df11bcd1c58281.tar.bz2 yosys-2b9c75f8e372f6886e073743d1df11bcd1c58281.zip | |
This PR should be the base for discussion, do not merge it yet!
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.
What it DOES'T do:
Detect registers connected to output ports of instances.
Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.
You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
Diffstat (limited to 'techlibs/.gitignore')
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