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author | Marcin KoĆcielnicki <marcin@symbioticeda.com> | 2019-09-27 11:03:04 +0200 |
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committer | Marcin KoĆcielnicki <koriakin@0x04.net> | 2019-09-27 18:34:12 +0200 |
commit | fd0e3a2c43d96ba31beede9865d5000230029994 (patch) | |
tree | 4a208618b2d7fa0cfbac4f2b45fa5f20a681f5a5 /passes | |
parent | 4b15cf5f76e2226bbce1a73d1e0ff54fbf093fe8 (diff) | |
download | yosys-fd0e3a2c43d96ba31beede9865d5000230029994.tar.gz yosys-fd0e3a2c43d96ba31beede9865d5000230029994.tar.bz2 yosys-fd0e3a2c43d96ba31beede9865d5000230029994.zip |
Fix _TECHMAP_REMOVEINIT_ handling.
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.
Fixes the problem identified in #1396.
Diffstat (limited to 'passes')
-rw-r--r-- | passes/techmap/techmap.cc | 30 |
1 files changed, 17 insertions, 13 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 1d0362ad6..08a1af2d5 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -935,19 +935,6 @@ struct TechmapWorker for (auto &it2 : it.second) if (!it2.value.is_fully_const()) log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value)); - if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_" && techmap_do_cache[tpl]) { - for (auto &it2 : it.second) { - auto val = it2.value.as_const(); - auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1)); - auto it = cell->connections().find(wirename); - if (it != cell->connections().end()) { - auto sig = sigmap(it->second); - for (int i = 0; i < sig.size(); i++) - if (val[i] == State::S1) - remove_init_bits.insert(sig[i]); - } - } - } techmap_wire_names.erase(it.first); } @@ -973,6 +960,23 @@ struct TechmapWorker mkdebug.off(); } + TechmapWires twd = techmap_find_special_wires(tpl); + for (auto &it : twd) { + if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_") { + for (auto &it2 : it.second) { + auto val = it2.value.as_const(); + auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1)); + auto it = cell->connections().find(wirename); + if (it != cell->connections().end()) { + auto sig = sigmap(it->second); + for (int i = 0; i < sig.size(); i++) + if (val[i] == State::S1) + remove_init_bits.insert(sig[i]); + } + } + } + } + if (extern_mode && !in_recursion) { std::string m_name = stringf("$extern:%s", log_id(tpl)); |