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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 00:24:23 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 00:31:08 -0700 |
| commit | fc9fb09a91220602538d99bfd08b1d8c34b69558 (patch) | |
| tree | 3752382917eb0cb83dec60109d76424dc3aa1014 /passes | |
| parent | 68b31f5e99e25c6bbd77af3d51c44bef88026c2f (diff) | |
| download | yosys-fc9fb09a91220602538d99bfd08b1d8c34b69558.tar.gz yosys-fc9fb09a91220602538d99bfd08b1d8c34b69558.tar.bz2 yosys-fc9fb09a91220602538d99bfd08b1d8c34b69558.zip | |
opt_clean: rminit without -purge; also remove if consistent with const..
warn otherwise
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_clean.cc | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 4e8492f7b..72ecc30e7 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -412,7 +412,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos return !del_wires_queue.empty(); } -bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose) +bool rmunused_module_init(RTLIL::Module *module, bool verbose) { bool did_something = false; CellTypes fftypes; @@ -445,9 +445,6 @@ bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose) for (auto wire : module->wires()) { - if (!purge_mode && wire->name[0] == '\\') - continue; - if (wire->attributes.count(ID::init) == 0) continue; @@ -464,11 +461,22 @@ bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose) if (wire_bit == mapped_wire_bit) goto next_wire; - if (qbits.count(sigmap(SigBit(wire, i))) == 0) - goto next_wire; + if (mapped_wire_bit.wire) { + if (qbits.count(mapped_wire_bit) == 0) + goto next_wire; - if (qbits.at(sigmap(SigBit(wire, i))) != init[i]) - goto next_wire; + if (qbits.at(mapped_wire_bit) != init[i]) + goto next_wire; + } + else { + if (mapped_wire_bit == State::Sx || mapped_wire_bit == State::Sz) + goto next_wire; + + if (mapped_wire_bit != init[i]) { + log_warning("Initial value conflict for wire '%s' and value '%s'.\n", log_signal(wire_bit), log_signal(mapped_wire_bit)); + goto next_wire; + } + } } if (verbose) @@ -512,7 +520,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool rmunused_module_cells(module, verbose); while (rmunused_module_signals(module, purge_mode, verbose)) { } - if (rminit && rmunused_module_init(module, purge_mode, verbose)) + if (rminit && rmunused_module_init(module, verbose)) while (rmunused_module_signals(module, purge_mode, verbose)) { } } |