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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-28 15:03:55 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-28 15:03:55 -0800 |
| commit | f505a41b7606c89289348d4c90a8ff85b3ede19a (patch) | |
| tree | 125c3b702ca30880f6639395ed024d5eac77b2b3 /passes | |
| parent | e2fc18f27b5e9f506724a486787c2106b9f7fb4f (diff) | |
| parent | 241901461ae02c6a41837e254088f277b8167476 (diff) | |
| download | yosys-f505a41b7606c89289348d4c90a8ff85b3ede19a.tar.gz yosys-f505a41b7606c89289348d4c90a8ff85b3ede19a.tar.bz2 yosys-f505a41b7606c89289348d4c90a8ff85b3ede19a.zip | |
Merge pull request #834 from YosysHQ/clifford/siminit
Add "write_verilog -siminit"
Diffstat (limited to 'passes')
0 files changed, 0 insertions, 0 deletions