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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:52:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:52:19 -0700 |
| commit | f0cadb0de801391083f6cc91d842e8137396b820 (patch) | |
| tree | 2609c298da4dbe34b35712909b18f15a732d156a /passes | |
| parent | bbc0e06af3db4da924a3a92ced85adc87cf6abb6 (diff) | |
| download | yosys-f0cadb0de801391083f6cc91d842e8137396b820.tar.gz yosys-f0cadb0de801391083f6cc91d842e8137396b820.tar.bz2 yosys-f0cadb0de801391083f6cc91d842e8137396b820.zip | |
Fix from merge
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 6c8527811..e9cdaf524 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1251,7 +1251,7 @@ struct Abc9Pass : public Pass { abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, false, "$", keepff, delay_target, lutin_shared, fast_mode, show_tempdir, box_file, lut_file, wire_delay, box_lookup, nomfs); - assign_map.set(mod); + assign_map.set(module); } design->selection_stack.pop_back(); design->selected_active_module.clear(); |